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Design and Implementation of a Low Power Ternary Full Adder

Printed in Malaysia Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803-5901 Phone: (504) 388-5622 Fax: (504) 388-5622 Email: ashok@.ee.lsu.edu (Received November 29, 1993, Revised April 26, 1995) In this work, the design and implementation of a low power are presented in CMOS technology. In a design, the basic building blocks, the positive ternary inverter () and negative ternary inverter () are developed using a CMOS inverter and pass transistors. In designs of and , W/L ratios of transistors have been varied for their omum performance. The and its building blocks have been simulated with SPICE 2G.6 using the MOSIS model parameters. The rise and fall times of show an improvement by a factor of 14 and 4, respectively, and that of the by a factor of nearly 4 and 17, respectively over that of earlier designs implemented in depletion-enhancement CMOS (DECMOS) technology. The noise margins improve by a factor of nearly 2 in and , respectively. The has been fabricated in MOSIS two micron n-well CMOS technology. The full adder and its building blocks, and have been tested experimentally for static and dynamic performance, compared with the SPICE simulated behavior, and close agreement is observed. The ternary-valued logic circuits designed in the present work which do not use depletion mode MOSFETS perform better than that implemented earlier in DECMOS technology. The present design is fully compatible with the current CMOS technology, uses fewer components and dissipates power in the microwatt range. Key Words: CMOS , Ternary Logic, 3-Valued Logic, Low Power CMOS Full Adder INTRODUCTION he performance of two levels (binary logic) is limited due to interconnect which occupies large area on a VLSI chip. In a VLSI circuit, approximately 70 percent of the area is devoted to interconnection, 20 percent to insulation, and 10 percent to devices 1 ]. One can achieve a more cost effective way of utilizing interconnections by using a larger set of signals over the same area in multiple-valued logic (MVL) circuits. This also solves the problem of pinout (the limit to the amount of data that can enter and exit a chip). Commercially multiple-valued logic circuits have made an appearance with the four-valued read-only memory (ROM) which Intel used in the control store of its 8087 numeric coprocessor ]. Hitachi has introduced into the market a 16-valued mass memory with a high storage capacity. Kameyama et al. [2] reported a 32 32 bit signed digit (SD) multiplier implementation using MVL circuits realized in current-mode CMOS technology. The chip area and power dissipation of MVL multiplier implementa75 tion reduced to half that of the fastest conveonal binary realization of the same multiplier. The main draw back in multiple valued logic circuits is that their design techniques are more complex than the binary logic circuits [3]. The implementation of MVL circuits have ranged through integrated injection logic, emitter coupled logic, CMOS and n-MOS technologies and charge-coupled devices. In this work, the design of ternary-valued logic circuits have been explored over other ternary-valued logic due to the following reasoning. In a numerical system, the number N is given by N R where R is the radix and d is the necessary number of digits up to the next highest integer value where necessary. If the cost or complexity C in any system is assumed to be proportional to R D [4], then C k(R d) k[R(ln N/In R)] where k is some constant. Differeating with respect to R will show that for a minimum cost C, R should be equal to e(2.718). Since in practice R must be an integer, this suggests that R 3(ternary) would be more economical than R ’ 2(binary) [4]. Several authors [5-9] have used CMOS integrated circuits for the realization of three-valued logic circuits. These designs have used power supply voltages higher than the MOSFETs threshold voltage which resulted in high power consumon in the circuits. Mouftah and Smith [10] have reported a family of loW-power threevalued CMOS circuits. In order to further reduce the power dissipation, increase the speed and eliminate the use of linear resistors in these circuits, Heung and Mouftah 11 proposed a design of ternary logic circuits based on the use of depletion enhancement complementary metal-oxide-semiconductor (DECMOS) technology. However, their implementation is not compatible with the current CMOS technology. The present CMOS technology does not use depletion mode transistors. The prime objective in our work is to minimize the number of transistors used, eliminate the use of resistors to lower the power consumon, reduce the propagation delay time and eliminate depletion mode transistors. The reduction in the number of transistors is our main focus as that enabled a more compact design which utilized the less chip area. The designs of positive ternary inverter (), negative ternary inverter () and simple ternary inverter (STI) are based on use of a CMOS inverter and pass transistors/CMOS transmission at its output. The pass transistors at the output of inverter have been used to pull the output node to the required voltage levels and also provide sufficient equivalent resistance for the ternary logic implementation. The two unary operators and have been used to design a Jk arithmetic circuit, and ternary (T-) which is esseally a multiplexer. Fourteen such T-s have been finally used in design of a . The design has been fabricated in MOSIS two micron CMOS n-well process, tested and performance verified. Q1 18/31 DIN Q2 Q3 (3/61 (3/221 C= FIGURE Positive ternary inverter. 2 DESIGN OF CMOS 3-VALUED LOGIC CIRCUITS Three types of basic ternary operations are defined by [11] Xc= 2 f C ifX=l X ifX 4:1 (1) C in Eq. (1) takes the values of logic 2 for a , logic for a STI and logic 0 for a which correspond to higher level (1), middle level (0) and lower level (-1), respectively. shows the schematic of a positive ternary Fig. inverter (). A p-MOSFET (Q3) is connected to the output of a standard CMOS inverter. Mouftah and Garba 12] have pointed out that by altering the length-to-width ratio of the PMOS and NMOS channels can significantly change the resistance of channels. Thus, the resistance of the circuit is directly proportional to its L/W ratio which can be effectively used to change the resistance of transistors to suit design needs. However, there is a lower limit to the value of L and W due to the limitations imposed by the design rules of the foundry which in the the of present case is W/L of 3/2. In Fig. p-MOSFET (Q3) has been tied to the negative power supply to keep it constantly turned on. A control signal, C of + IV is applied to the source of p-MOSFET (Q3). The W/L ratio of p- and n-MOSFETs (Q1 and Q2) in CMOS inverter are 10/3 and 3/6, respectively, and that of p-MOSFET (Q3) connected to the output is 3/22. The p-MOSFET (Q3) pulls the output of the CMOS inverter to + 1V during the cycle where both transistors of the inverter are nearly in cut-off. Fig. 2 shows the schematic of a negative ternary inverter (). An n-MOSFET (Q3) is connected to the output of a CMOS inverter with its tied to the positive power supply to keep it constantly turned on. A control signal, C of is applied to the source of n-MOSFET(Q 3) and that pulls the output of CMOS inverter to that value. The CMOS inverter is forced to a value of in phase where both transistors of the CMOS inverter are in the cut-off region. The W/L ratio of p- and n-MOSFET (Q1 and Q2) comprising the CMOS inverter are 19/3 and 12/3, respectively and that of n-MOSFET(Q 3) connected to the output is 6/23. The /3) _6/23) aids in pulling up a control signal, C of 0V to the output when the inverter is in cut-off. Figures 4 and 5 show the circuits for ternary NAND and ternary NOR, respectively. They are designed by connecting a CMOS transmission to the common drain output of a binary CMOS NAND and NOR. The s of p- and n-MOSFETs (Q5 and Q6) in the transmission are tied to negative and positive power supplies, respectively. It can be seen from the Fig. 4 for ternary NAND that the transmission at the output helps pull the output to 0V when transistors (Q, Q2, Q3 and Q4) are in cut-off. This happens in cases when inputs 0, X 0, Y 0; X 0, Y 1; andX 1, Y respectively. Similary operation of ternary NOR for the Fig. 5 can be explained. The output pulls to 0V when X 0, Y 0, Y 0, -1, Y -1; andX 0;X respectively. 3 DESIGN FIGURE 2 Negative ternary inverter. value of 6/23 was chosen for W/L ratio so as to make it more resistive and avoid the pass transistor to latch the output of the whole circuit to . Fig. 3 shows the schematic of a simple ternary inverter (STI) designed by connecting a CMOS transmission to the common drain output of a CMOS inverter. The s of p- and n- MOSFETs (Q3 and Q4) in the transmission are tied to negative and positive power supplies, respectively. The W/L ratio of p- and nMOSFETs (Q and Q2) are 77/3 and 75/3, respectively and the corresponding values of transistors (Q3 and Q4) in transmission are 3/3 for both. The transmission A is a circuit that will add two trits and a previous carry trit, and generate a sum trit and a carry trit (a tilt is equivalent of a bit in a binary system). It can be implemented by using two ternary half adders and a binary OR by analogy with the typical binary full adder. The advantage of multiple-valued carry ripple adders is in fact that the carry is always binary. Since the carry propagation makes up most of the delay in a carry ripple adder, this suggests that a multiple-valued adder could have a speed advantage over its binary counterpart because each digit carries more information than the binary case 13]. In the present design, the full adder is composed of fourteen T-s which are esseally multiplexers. Each T- is further composed of a Jk {) Q1 OUTPUT FIGURE 3 Simple ternary inverter. FIGURE 4 Ternary NAND circuit. l-" OUTPUT =!V Q6 switch that has inputs Y l, Y2, Y3, respectively. The value of input to the Jk arithmetic circuit determines which one of the signals (Yl, Y2, Y3) will be steered to the output thus functioning as a multiplexer. The full adder comprises of fourteen T-s as shown in Fig. 8. Since the Jg arithmetic circuit part of the T- is common, we can effectively reduce the component count by making it common for three stages. The area occupied by the ternary adder as a whole can be conserved in this way. The complete has been simulated using SPICE 2G.6 and the corresponding truth table is summarized in Table 1. 4 DESIGN VERIFICATION AND DISCUSSION The design was fabricated in MOSIS two micron CMOS n-well process. The static and dynamic performance of the device were studied experimentally and compared with the corresponding. SPICE 2G.6 simulation. Averaged Level 2 MOSFET model parameters from MOSIS were used and are summarized in Tables 2 and 3, respectively. Figures 9(a) and (b) show the voltage transfer characteristics of and obtained from SPICE 2G.6 simulation, measurements, and Ref. 11, respectively. It can be seen from Figs. 9(a) and (b) that measured and characteristics have close agreements with the corresponding SPICE 2G.6 simulation. The present design of and also exhibit sharper voltage transfer characteristics compared to designs in Ref. 11. FIGURE 5 Ternary NOR circuit. arithmetic circuit. The Jk arithmetic 1 -1 function is defined by Jk(X) ifX=l if X 4: k (2) where k can take values of logic 0, logic and logic 2 which corresponds to higher level (1), middle level (0) and lower level (- 1), respectively. The block diagram of a Jk arithmetic circuit is shown in Fig. 6 which uses the logic design described in Ref. 13. The design of the T- circuit is based on the J arithmetic circuit. The function of the T- is described as follows 11 T(Yl, Y2, Y3;X) Yi (3) where will take a value of if X takes the value of -1, 2 if X is 0, and 3 if X is 1. The block diagram of a T- is shown in Fig. 7. Each ternary switch consists of a p-channel and n-channel enhancement transistor. The source of p-channel MOSFET is connected to the drain of n-channel MOSFET and vice versa. A control signal, C controls the n-channel MOSFET directly, and the p-channel MOSFET is controlled by C. When C is equal to + 1V the switch will be on, for C equal to -1V the switch will be off. The J-l, Jo, J signals of the Jk arithmetic circuits are connected to C of the ternary d_l Jk Jo Jl Inverter TS -I .IX) Buffer Ternary Multiplexer (TM) FIGURE 6 Block diagram of a Jk arithmetic circuit. FIGURE 7 A ternary T-. Table 4 summarizes noise margins corresponding to and , respectively. It can be seen from the Table 4 that significant improvement in noise margins in and is observed over the corresponding designs in Ref. 11. Table 5 summarizes simulated rise time (tr), fall time (tf) of and , respectively, and propagation delay times (tpLH, tpHL) of circuit. The simulated transient behavior of these circuits are compared with corresponding circuits implemented in DECMOS technology 11 for 0 pF and 15 pF equivalent load capacitance, Cz: and unbuffered circuit conditions. It can be seen from Table 5 that the rise and fall times of shows an improvement by a factor of 14 and 4 and that of by a factor of nearly 4 and 17, respectively over that of earlier designs implemented in DECMOS technology. It is also seen in Table 5 that the present full adder design performs better than the counterpart DECMOS design. The fabricated device was tested for its performance evaluation and meets the required logic levels of summarized in Table 1. The and circuits were tested under pulse transient conditions with an equivalent 15pF load capacitance, Cz and compared with the corresponding simulations. The results are summarized in Table 5 for Cz 15pE The 15pF load capacitance corresponds to a 15pF input capacitance to the TEK 2467B oscilloscope used in the measurement which acts as a load to the device under test. It is seen from Table 5 that the measured values are in good agreement with the corresponding values obtained from simulations. The power dissipation calculated from SPICE is summarized in Table 6 for , and , respectively. It is noticed that both designs in the present work and Ref. 11 exhibit power consumon in the microwatt power range. It is worth meoning that the present design uses nearly one half of the silicon area of Ref. 11 for the design of a circuit. FIGURE 8 A . TABLE Truth table of a derived from SPICE simulation ci Co -1 -1 0 0 -0 0 5 CONCLUSIONS A has been designed using fourteen T-s and implemented in MOSIS two micron CMOS n-well process. The T- uses a Jk arithmetic circuit and three ternary switches. The Jk arithmetic circuit mainly consists of and apart from NOR, inverter and buffer circuits. The and have been designed using an inverter and pass-transistors at its output. The design of and is fully compatible with the MOSIS two micron CMOS n-well process. It is shown that the performance -1 -1 LD 0.24974U VTO 0.94 PHI 0.6 UCRIT XJ 0.25U NEFF RSH 27.36 CGBO 4.96808E- 10 CJSW 3.9772E-10 TABLE 2 Averaged SPICE NMOS model parameters NMOS Parameters TOX 421.00001E-10 KP 5.504E-5 UO 628.787 DELTA 1.041739E-5 LAMBDA 1.67204E-2 NSS 1El0 CGDO 3.283127E-10 CJ 4.1066E-4 MJSW 0.334688 NSUB 2.296064E16 GAMMA 0.9961 UEXP 0.22018 VMAX 83151.5 NFS 2.509221E12 TPG CGSO 3.28322E-10 MJ 0.467277 PB 0.8 LD 0.25000U VTO 0.96 PHI 0.6 UCRIT 21136.5 XJ 0.25U NEFF 1.001 RSH 70.00 CGBO 4.75120E-10 CJSW 1.9981E- 10 TABLE 3 Averaged SPICE PMOS model parameters PMOS Parameters TOX 421.00001E-10 KP 2.296E-5 UO 262.000 DELTA .721685 LAMBDA 5.597E-2 NSS 1El0 CGDO 3.286622E-10 CJ 12.0692E-4 MJSW 0.177313 NSUB 5.917000E15 GAMMA 0.5057 UEXP 0.22505 VMAX 41563.6 NFS 8.0389Ell TPG CGSO 3.28322E-10 MJ 0.431872 PB 0.7 of , and implemented in CMOS technology closely matches with designs implemented in corresponding DECMOS technology. There is very good agreement between simulated and measured voltage transfer characteristics, noise margins and transient times for , and , respectively. A descrion of the design of ternary NOR, ternary NAND and simple ternary inverter without using depletion mode transistors and resistors are also included for completeness. In the low power design range, the present design of ternary circuits uses lesser number of components and thereby reducing the chip area to nearly one half compared to designs of DECMOS technology. Furthermore, 1.0l the use of depletion mode devices in the present work has been eliminated. In the present work, the design of and its building blocks are designed within the limitation of the MOSIS foundry for the fabrication such as the non-availability of process modification to vary threshold voltages of MOSFETS. However, the present design could be further improved with the flexibility in process modification. Acknowledgements Authors are very grateful to the reviewers for their valuable comments and suggestions. o Simulated Measured [] Ref. 11 Simulated Measured Ref. 11 -1,01 INPUT VOLTAGE, V "!’-"1.0O INPUT VOLTAGE, FIGURE 9 (a). Voltage transfer characteristics of a . FIGURE 9 (b). Voltage transfer characteristics of a . TABLE 4 Noise margins characteristics Noise Margin, Volts 1--1 -1 -1 Present Work Measured Ref. 11 [3] S.L. Hurst, "Two decades of multiple valued logic--an invited tutorial," in Proceedings of IEEE International Symposium on Multiple-Valued Logic, p. 164, May 1988. [4] S.L. Hurst, "Multiple-valued logic--its status and its future," IEEE Transactions on Computers, vol. C-33, no. 12, pp. 1160-1179, December 1984. [5] H.T. Mouftah and I.B. Jordan, "Integrated circuits for ternary logic," in Proc. ISMVL-74, (Morgantown, WV), pp. 285-302, Present Work May 1974. [6] H.T. Mouftah and I.B. Jordan, "Design of ternary COS/MOS memory and sequeal circuits," IEEE Trans. Computers, vol. C-26, pp. 281-288, March 1977. [7] H.T. Mouftah, "A study on the implementation of three-valued logic," in Proc. ISMVL-76, (Bloomington, IL), pp. 123-126, May 1976. [8] J.M. Carmona, J.L. Huertas, and J.I. Acha, "Realization of three-valued C.M.O.S. cycling s," Electron. Lett., vol. 14, pp. 288-290, 1978. [9] H.T. Koanantakool, "Implementation of ternary idefy cell using CMOS integrated circuits," Electron. Lett., vol. 14, pp. 462-464, 1978. [10] H.T. Mouftah and K.C. Smith, "Injected voltage low-power CMOS for 3-valued logic," lEE Proceedings, vol. 129, pt. G, no. 6, pp. 270-271, December 1982. [11] A. Heung and H.T. Mouftah, "Depletion/enhancement CMOS for a low power family of three-valued logic circuits," IEEE Journal of Solid-State Circuits, vol. SC-20, no. 2, pp. 609-615, April 1985. [12] H.T. Mouftah and A.I. Garba, "VLSI implementation of a 5- trit full adder," lEE Proceedings, vol. 131, pt. G, pp. 214-220, October 1984. Measured Ref. 11 TABLE 5 Transient times Load (C., pF) tr, ns(10-90%) --1 --1 5 70 405 400 15" 50* 474 458 I, ns(90-10%) 1--1 4 70 210 223 22** 83** 739 714 Ternary Full Adder *tpLH **tpLH TABLE 6 Power dissipation. Power dissipation Ref. 11 Present work 0.8 nW 1.97 lamW 29 nW 12 laW [13] H.M. Razavi and S.E. Bou-Ghazale, "Design of a fast CMOS ternary adder," in Proceedings of IEEE International Symposium on Multiple-Valued Logic, p. 20, May 1987. Biographies A. SRIVASTAVA has served as a sciest at the Central Electronics Engineering Research Institute, Pilani; and on the faculty of Birla Institute of Technology and Science, Pilani, India; North Carolina State University; State University of New York; University of Cincinnati and as a UNESCO Fellow; as a visiting sciest and UNESCO Fellow at the University of Arizona. Currently he is an Associate Professor of Electrical and Computer Engineering at the Louisiana State University in Baton Rouge. His research interests include CMOS/BiCMOS VLSI design and device modeling, cryogenic CMOS electronics, smart gas sensors and MEMS. His e-mail address is ashok@.ee.lsu.edu. laW laW *Power dissipation obtained using SPICE model parameters of Tables 2 and 3. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

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