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VLSI Package Reliability

VLSI Package Reliability The challenge presented by advanced package development in the past five years has further accentuated the constant need for package quality and reliability monitoring through extensive laboratory testing and evaluation. As pin counts and chip geometries have continued to increase, there has been additional pressure from the military and commercial sectors to improve interconnect designs for packaged chips, including chips directly attached to the printed wiring board PWB. One of the options employed has been tape automated bonding TAB. However, this assembly technique also presents new standardisation, qualification and reliability problems. Therefore, at Rome Air Development Center RADC, there is regular assessment through inhouse failure analysis studies of parts destined for military and space systems. In addition, Department of Defense DoD high tech development programmes, such as very high speed integrated circuits VHSIC, have utilised all present screening methods for package evaluation, and have addressed the need for development of more definitive nondestructive tests. To answer this need, two RADC contractual efforts were awarded on laser thermal and ultrasonic inspection techniques. Through these package evaluations, a number of potential reliability problems are identified and the results provided to the specific contractors for corrective action implementation. Typical problems uncovered are lid material and pin corrosion, damage to external components and adhesion problems between copper leads and polyimide supports, hermeticity failures, high moisture content in sealed packages and particle impact noise detection PIND test failures internal particles. Further tests uncover bond strength failures, bond placement irregularities, voids in die attach material potential heat dissipation problems, and die surface defects such as scratches and cracks. This presentation will review the specific package level physical test methods that are employed as a means of evaluating reliable package performance. Many of the tests, especially the environmental testse.g., salt atmosphere and moisture resistanceprovide accelerated forms of anticipated conditions and are therefore applied as destructive tests to assess package quality and reliability in field use. In addition to a manufacturer's compliance with designated qualification procedures, the key to package quality lies in utilising good materials and wellcontrolled assembly techniques. This practice, along with effective package screen tests, will ensure reliable operation of very large scale integration VLSI devices in severe military and commercial environment applications. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Microelectronics International Emerald Publishing

VLSI Package Reliability

Speicher, P.S.
Microelectronics International , Volume 8 (3): 7 – Mar 1, 1991
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References (8)

Publisher
Emerald Publishing
Copyright
Copyright © Emerald Group Publishing Limited
ISSN
1356-5362
DOI
10.1108/eb044454
Publisher site
See Article on Publisher Site

Abstract

The challenge presented by advanced package development in the past five years has further accentuated the constant need for package quality and reliability monitoring through extensive laboratory testing and evaluation. As pin counts and chip geometries have continued to increase, there has been additional pressure from the military and commercial sectors to improve interconnect designs for packaged chips, including chips directly attached to the printed wiring board PWB. One of the options employed has been tape automated bonding TAB. However, this assembly technique also presents new standardisation, qualification and reliability problems. Therefore, at Rome Air Development Center RADC, there is regular assessment through inhouse failure analysis studies of parts destined for military and space systems. In addition, Department of Defense DoD high tech development programmes, such as very high speed integrated circuits VHSIC, have utilised all present screening methods for package evaluation, and have addressed the need for development of more definitive nondestructive tests. To answer this need, two RADC contractual efforts were awarded on laser thermal and ultrasonic inspection techniques. Through these package evaluations, a number of potential reliability problems are identified and the results provided to the specific contractors for corrective action implementation. Typical problems uncovered are lid material and pin corrosion, damage to external components and adhesion problems between copper leads and polyimide supports, hermeticity failures, high moisture content in sealed packages and particle impact noise detection PIND test failures internal particles. Further tests uncover bond strength failures, bond placement irregularities, voids in die attach material potential heat dissipation problems, and die surface defects such as scratches and cracks. This presentation will review the specific package level physical test methods that are employed as a means of evaluating reliable package performance. Many of the tests, especially the environmental testse.g., salt atmosphere and moisture resistanceprovide accelerated forms of anticipated conditions and are therefore applied as destructive tests to assess package quality and reliability in field use. In addition to a manufacturer's compliance with designated qualification procedures, the key to package quality lies in utilising good materials and wellcontrolled assembly techniques. This practice, along with effective package screen tests, will ensure reliable operation of very large scale integration VLSI devices in severe military and commercial environment applications.

Journal

Microelectronics International – Emerald Publishing

Published: Mar 1, 1991

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