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Translation rules of SysML state machine diagrams into CSP# toward formal model checking

Translation rules of SysML state machine diagrams into CSP# toward formal model checking Purpose – This study aims to describe the behavior of blocks in the system under consideration using systems modeling language (SysML) state machine diagrams. In this paper, formalization and model checking for SysML state machine diagrams have been investigated. Design/methodology/approach – The work by Zhang and Liu (2010) proposed a formalization of SysML state machine diagrams in which the diagrams were translated into CSP# processes that could be verified by the state‐of‐the‐art model checker PAT. In this paper, several modifications have been made and new rules have been added to the translation described in that work. Findings – First, three translation rules were modified, which apparently are inappropriately defined according to the SysML definition of state machine diagrams. Next, we add new translation rules for two components of the diagrams – junction and choice pseudostates – which have not been dealt with previously. Further, we are implementing the automatic translation system on a web‐based model‐driven development tool, which reflects on our translation rules. Originality/value – As the contribution of this work, more reasonable verification results for more general SysML state machine diagrams can be achieved. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png International Journal of Web Information Systems Emerald Publishing

Translation rules of SysML state machine diagrams into CSP# toward formal model checking

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Publisher
Emerald Publishing
Copyright
Copyright © 2014 Emerald Group Publishing Limited. All rights reserved.
ISSN
1744-0084
DOI
10.1108/IJWIS-02-2014-0004
Publisher site
See Article on Publisher Site

Abstract

Purpose – This study aims to describe the behavior of blocks in the system under consideration using systems modeling language (SysML) state machine diagrams. In this paper, formalization and model checking for SysML state machine diagrams have been investigated. Design/methodology/approach – The work by Zhang and Liu (2010) proposed a formalization of SysML state machine diagrams in which the diagrams were translated into CSP# processes that could be verified by the state‐of‐the‐art model checker PAT. In this paper, several modifications have been made and new rules have been added to the translation described in that work. Findings – First, three translation rules were modified, which apparently are inappropriately defined according to the SysML definition of state machine diagrams. Next, we add new translation rules for two components of the diagrams – junction and choice pseudostates – which have not been dealt with previously. Further, we are implementing the automatic translation system on a web‐based model‐driven development tool, which reflects on our translation rules. Originality/value – As the contribution of this work, more reasonable verification results for more general SysML state machine diagrams can be achieved.

Journal

International Journal of Web Information SystemsEmerald Publishing

Published: Jun 10, 2014

Keywords: SysML state machine diagrams; Formal semantics; Model checking; CSP#

References