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Techniques of impedance matching for minimal PCB channel loss at 40 GBPS signal transmission

Techniques of impedance matching for minimal PCB channel loss at 40 GBPS signal transmission This paper aims to analyze the negative impact of surface mount (SMT) pad and imperfect via structure such as stub, pad, non-functional pad (NFP) and anti-pad on the signal integrity at 40 Gbps transmission on printed circuit board (PCB) due to impedance mismatch or discontinuity. The optimized modeling of via and SMT structures is performed to achieve minimal impedance mismatch and insertion loss less than 10 dB for six-inch full path transmission line between transmitter and receiver on PCB at Nyquist frequency 20 GHz.Design/methodology/approachThis work is split into two phases. The first phase involves optimization of via and SMT structures in three-dimensional electromagnetic (3DEM) simulation using Hyperlynx Via Wizard and Keysight EMPro software, respectively, followed by analysis of time domain reflectometry (TDR) and insertion loss (Sdd21). Whereas, in the second phase, full path hybrid mode simulation involving vias for signal layer transition, a 6-inch PCB channel and SMT pads is performed using Keysight ADS software to observe the TDR, Sdd21 and eye diagram at 40 Gbps transmission.FindingsImperfect via and SMT structures have a negative effect on signal reflection and attenuation. The optimized via and SMT minimizes the impedance mismatch by 81 per cent and insertion loss by 4.5 dB, ultimately enlarging the eye diagram opening to achieve minimal data loss at receiver with 40 Gbps transmission.Originality/valueThe results of original empirical research work on signal integrity analysis that optimizes the PCB channel design to achieve 40 Gbps signal transmission are presented in this study. It serves as a reference guide for high-speed PCB layout design. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Circuit World Emerald Publishing

Techniques of impedance matching for minimal PCB channel loss at 40 GBPS signal transmission

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Publisher
Emerald Publishing
Copyright
© Emerald Publishing Limited
ISSN
0305-6120
DOI
10.1108/cw-01-2019-0004
Publisher site
See Article on Publisher Site

Abstract

This paper aims to analyze the negative impact of surface mount (SMT) pad and imperfect via structure such as stub, pad, non-functional pad (NFP) and anti-pad on the signal integrity at 40 Gbps transmission on printed circuit board (PCB) due to impedance mismatch or discontinuity. The optimized modeling of via and SMT structures is performed to achieve minimal impedance mismatch and insertion loss less than 10 dB for six-inch full path transmission line between transmitter and receiver on PCB at Nyquist frequency 20 GHz.Design/methodology/approachThis work is split into two phases. The first phase involves optimization of via and SMT structures in three-dimensional electromagnetic (3DEM) simulation using Hyperlynx Via Wizard and Keysight EMPro software, respectively, followed by analysis of time domain reflectometry (TDR) and insertion loss (Sdd21). Whereas, in the second phase, full path hybrid mode simulation involving vias for signal layer transition, a 6-inch PCB channel and SMT pads is performed using Keysight ADS software to observe the TDR, Sdd21 and eye diagram at 40 Gbps transmission.FindingsImperfect via and SMT structures have a negative effect on signal reflection and attenuation. The optimized via and SMT minimizes the impedance mismatch by 81 per cent and insertion loss by 4.5 dB, ultimately enlarging the eye diagram opening to achieve minimal data loss at receiver with 40 Gbps transmission.Originality/valueThe results of original empirical research work on signal integrity analysis that optimizes the PCB channel design to achieve 40 Gbps signal transmission are presented in this study. It serves as a reference guide for high-speed PCB layout design.

Journal

Circuit WorldEmerald Publishing

Published: Aug 21, 2019

Keywords: SMT; Signal integrity; Eye diagram; TDR; Sdd21; Via

References