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Stress analysis and structural optimization of 3-D IC package based on the Taguchi method

Stress analysis and structural optimization of 3-D IC package based on the Taguchi method PurposeThe transistor circuit based on Moore's Law is approaching the performance limit. The three-dimensional integrated circuit (3-D IC) is an important way to implement More than Moore. The main problems in the development of 3-D IC are Joule heating and stress. The stresses and strains generated in 3-D ICs will affect the performance of electronic products, leading to various reliability issues. The intermetallic compound (IMC) joint materials and structures are the main factors affecting 3-D IC stress. The purpose of this paper is to optimize the design of the 3-D IC.Design/methodology/approachTo optimize the design of 3-D IC, the numerical model of 3-D IC was established. The Taguchi experiment was designed to simulate the influence of IMC joint material, solder joint array and package size on 3-D IC stress.FindingsThe simulation results show that the solder joint array and IMC joint materials have great influence on the equivalent stress. Compared with the original design, the von Mises stress of the optimal design was reduced by 69.96 per cent, the signal-to-noise ratio (S/N) was increased by 10.46 dB and the fatigue life of the Sn-3.9Ag-0.6Cu solder joint was increased from 415 to 533 cycles, indicating that the reliability of the 3-D IC has been significantly improved.Originality/valueIt is necessary to study the material properties of the bonded structure since 3-D IC is a new packaging structure. Currently, there is no relevant research on the optimization design of solder joint array in 3-D IC. Therefore, the IMC joint material, the solder joint array, the chip thickness and the substrate thickness are selected as the control factors to analyze the influence of various factors on the 3-D IC stress and design. The orthogonal experiment is used to optimize the structure of the 3-D IC. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Soldering & Surface Mount Technology Emerald Publishing

Stress analysis and structural optimization of 3-D IC package based on the Taguchi method

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Publisher
Emerald Publishing
Copyright
Copyright © Emerald Group Publishing Limited
ISSN
0954-0911
DOI
10.1108/ssmt-04-2019-0016
Publisher site
See Article on Publisher Site

Abstract

PurposeThe transistor circuit based on Moore's Law is approaching the performance limit. The three-dimensional integrated circuit (3-D IC) is an important way to implement More than Moore. The main problems in the development of 3-D IC are Joule heating and stress. The stresses and strains generated in 3-D ICs will affect the performance of electronic products, leading to various reliability issues. The intermetallic compound (IMC) joint materials and structures are the main factors affecting 3-D IC stress. The purpose of this paper is to optimize the design of the 3-D IC.Design/methodology/approachTo optimize the design of 3-D IC, the numerical model of 3-D IC was established. The Taguchi experiment was designed to simulate the influence of IMC joint material, solder joint array and package size on 3-D IC stress.FindingsThe simulation results show that the solder joint array and IMC joint materials have great influence on the equivalent stress. Compared with the original design, the von Mises stress of the optimal design was reduced by 69.96 per cent, the signal-to-noise ratio (S/N) was increased by 10.46 dB and the fatigue life of the Sn-3.9Ag-0.6Cu solder joint was increased from 415 to 533 cycles, indicating that the reliability of the 3-D IC has been significantly improved.Originality/valueIt is necessary to study the material properties of the bonded structure since 3-D IC is a new packaging structure. Currently, there is no relevant research on the optimization design of solder joint array in 3-D IC. Therefore, the IMC joint material, the solder joint array, the chip thickness and the substrate thickness are selected as the control factors to analyze the influence of various factors on the 3-D IC stress and design. The orthogonal experiment is used to optimize the structure of the 3-D IC.

Journal

Soldering & Surface Mount TechnologyEmerald Publishing

Published: Jan 1, 1

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