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References (7)
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P. Chan, K. Karplus (1989)
Computing Signal Delay in General RC Networks by Tree/Link Partitioning26th ACM/IEEE Design Automation Conference
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J. Rubinstein, P. Penfield, M. Horowitz (1983)
Signal delay in RC tree networksPapers on Twenty-five years of electronic design automation
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C. Marinov, P. Neittaanmäki (1989)
Global delay time for general distributed networks with applications to timing analysis of digital MOS integrated circuitsCompel-the International Journal for Computation and Mathematics in Electrical and Electronic Engineering, 8
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10.1109/TCAD.1983.1270037
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10.1109/43.57781
-
10.1007/978-94-011-3440-8
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10.1007/978-1-4612-5282-5
- Publisher
- Emerald Publishing
- Copyright
- Copyright © Emerald Group Publishing Limited
- ISSN
- 0332-1649
- DOI
- 10.1108/eb010114
- Publisher site
- See Article on Publisher Site
Abstract
A network composed by RC distributed parameter lines with resistively grounded nodes is considered. Upper and lower bounds for the transient voltages are inferred. The results are of interest for the signal delay evaluation in VLSI interconnections. A numerical example is presented.
Journal
COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering – Emerald Publishing
Published: Apr 1, 1992