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Optimization of 1-µm gate length InGaAs-InAlAs pHEMT

Optimization of 1-µm gate length InGaAs-InAlAs pHEMT The purpose of this study is to demonstrate a pseudomorphic High Electron Mobility Transistor (pHEMT) cutoff frequency (fT) and maximum oscillation frequency (fmax) are determined by the role of its gate length (Lg). Theoretically, to obtain an Lg of 1 µm, the gate’s resist opening must be 1 µm wide. However, after the coat-expose-develop (C-E-D) process, the Lg became 13% larger after metal evaporation. This enlargement is due to both resist thickness and its profile.Design/methodology/approachThis research aims to optimize the 1-µm Lg InGaAs-InAlAs pHEMT C-E-D process, where the diluted AZ®nLOF™ 2070 resist with AZ® EBR solvent technique has been used to solve the Lg enlargement problem. The dilution theoretically allows the changing of a resist thickness to different film thickness using the same coating parameters. Here, for getting a new resist, which is simply called AZ 0.5 µm, the experiment’s important parameters such as the coater’s spin speed of 3,000 rpm and soft bake at 110°C for 5 min are executed.FindingsThe newly mixed AZ 0.5 µm resist has presented a high resolution and undercut profile rather than standard AZ 1 µm resist. Hence, the Lg metallization after using AZ 0.5 µm optimized process showed better results than AZ 1 µm which used the standard process.Originality/valueThe outcome of the optimization has reached that it is possible to get a nearly sub-µm range gate’s opening using a diluted resist, and at the same time retaining a high resolution and undercut profile. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Microelectronics International Emerald Publishing

Optimization of 1-µm gate length InGaAs-InAlAs pHEMT

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Publisher
Emerald Publishing
Copyright
© Emerald Publishing Limited
ISSN
1356-5362
eISSN
1356-5362
DOI
10.1108/mi-03-2022-0044
Publisher site
See Article on Publisher Site

Abstract

The purpose of this study is to demonstrate a pseudomorphic High Electron Mobility Transistor (pHEMT) cutoff frequency (fT) and maximum oscillation frequency (fmax) are determined by the role of its gate length (Lg). Theoretically, to obtain an Lg of 1 µm, the gate’s resist opening must be 1 µm wide. However, after the coat-expose-develop (C-E-D) process, the Lg became 13% larger after metal evaporation. This enlargement is due to both resist thickness and its profile.Design/methodology/approachThis research aims to optimize the 1-µm Lg InGaAs-InAlAs pHEMT C-E-D process, where the diluted AZ®nLOF™ 2070 resist with AZ® EBR solvent technique has been used to solve the Lg enlargement problem. The dilution theoretically allows the changing of a resist thickness to different film thickness using the same coating parameters. Here, for getting a new resist, which is simply called AZ 0.5 µm, the experiment’s important parameters such as the coater’s spin speed of 3,000 rpm and soft bake at 110°C for 5 min are executed.FindingsThe newly mixed AZ 0.5 µm resist has presented a high resolution and undercut profile rather than standard AZ 1 µm resist. Hence, the Lg metallization after using AZ 0.5 µm optimized process showed better results than AZ 1 µm which used the standard process.Originality/valueThe outcome of the optimization has reached that it is possible to get a nearly sub-µm range gate’s opening using a diluted resist, and at the same time retaining a high resolution and undercut profile.

Journal

Microelectronics International – Emerald Publishing

Published: Jan 2, 2023

Keywords: HEMT; Gate length; High breakdown; Metal evaporation; Semiconductor device; Sub-um

References

  • DC and RF characteristics of 20 nm gate length InAlAs/InGaAs/InP HEMTs for high frequency application
    Boursali, A.; Guen-Bouazza, A.; Sayah, C.
  • Photoresist technology for 0.25 um lithography
    Conley, W.
  • Wet etching of p-GaN for crystallographically smooth vertical sidewalls
    Hsu, J.Y.S.
  • InP/InAlAs/InGaAs HEMTs for high speed and low power applications
    Jaiswal, N.K.; Ramakrishnan, V.N.
  • Optimization of empirical modelling of advanced highly strained In0.7Ga0.3As/In0.52Al0.48As pHEMTs for low noise amplifier
    Jubadi, W.M.; Packeer, F.; Missous, M.
  • Fabrication and characterization of tensile In0.3Al0.7As barrier and compressive In0.7Ga0.3As channel pHEMTs having extremely low gate leakage for low-noise applications
    Packeer, F.; Isa, M.M.; Jubadi, W.M.; Ian, K.W.; Missous, M.
  • Structural asymmetry induced nonmonotonic electron mobility in pseudomorphic double quantum well high electron mobility transistor structure
    Panda, A.K.; Panda, S.R.; Sahu, A.; Das, S.; Sahu, T.
  • III–V heterostructure devices for high-frequency applications
    Saravanakumar, R.
  • The effect of align parameter on scattering parameter for pseudomorphic high electron mobility transistor
    SATILMIŞ, G.