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Optimal placement of modules on partially reconfigurable device for reconfiguration time improvement

Optimal placement of modules on partially reconfigurable device for reconfiguration time improvement Purpose – The purpose of this paper is to reduce the reconfiguration time of a field‐programmable gate array (FPGA). Design/methodology/approach – The paper focuses on introducing a new temporal placement algorithm which uses a typical mathematical formalism to optimize the reconfiguration time. Findings – Results show that the algorithm decreases considerably the reconfiguration time compared with famous temporal placement algorithms. Originality/value – The paper proposes a new temporal placement algorithm which optimizes reconfiguration time of modules on the device. The studied evaluation cases show that the proposed algorithm provides very significant results in terms reconfiguration time of modules versus other well‐known algorithms used in the temporal placement field. The authors uses the eigenvalue of the Laplacian matrix. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Microelectronics International Emerald Publishing

Optimal placement of modules on partially reconfigurable device for reconfiguration time improvement

Bouraoui Ouni; Abdellatif Mtibaa
Microelectronics International , Volume 29 (2): 7 – May 4, 2012
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Publisher
Emerald Publishing
Copyright
Copyright © 2012 Emerald Group Publishing Limited. All rights reserved.
ISSN
1356-5362
DOI
10.1108/13565361211237707
Publisher site
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Abstract

Purpose – The purpose of this paper is to reduce the reconfiguration time of a field‐programmable gate array (FPGA). Design/methodology/approach – The paper focuses on introducing a new temporal placement algorithm which uses a typical mathematical formalism to optimize the reconfiguration time. Findings – Results show that the algorithm decreases considerably the reconfiguration time compared with famous temporal placement algorithms. Originality/value – The paper proposes a new temporal placement algorithm which optimizes reconfiguration time of modules on the device. The studied evaluation cases show that the proposed algorithm provides very significant results in terms reconfiguration time of modules versus other well‐known algorithms used in the temporal placement field. The authors uses the eigenvalue of the Laplacian matrix.

Journal

Microelectronics International – Emerald Publishing

Published: May 4, 2012

Keywords: Integrated circuits; Programming and algorithm theory; Micro‐circuit technology; Multi chip modules

References

  • Hardware module placement for dynamically reconfigurable architecture
    Albouchi, A.; Ayadi, R.; Ouni, B.; Mtibaa, A.
  • Speeding up online placement for XILINX FPGAs by reducing configuration overhead
    Ali, A.; Jürgen, T.
  • New approach for on‐line placement on reconfigurable devices
    Ali, A.; Christophe, B.; Marcus, B.; Jurgen, T.
  • Introduction to reconfigurable computing architectures, algorithms, and applications
    Christophe, B.
  • Non‐preemptive multitasking on FPGAs: task placement and footprint transform
    Herbert, W.; Marco, P.
  • Dynamic reconfiguration to support concurrent applications
    Jack, S.; Jean, N.; Karen, T.; Vikram, Y.; Jignesh, S.; Robert, C.
  • Defragmenting the module layout of a partially reconfigurable device
    Jan, C.; Fekete, P.; Majer, M.; Ali, A.; Christophe, B.; Frank, H.; Jurgen, T.
  • Fast template placement for reconfigurable computing systems
    Kiarash, B.; Ryan, K.; Majid, S.
  • Combining temporal partitioning and temporal placement techniques for communication cost improvement
    Ouni, B.; Aydi, R.; Mtibaa, A.
  • Fast online task placement on FPGAs: free space partitioning and 2‐D hashing
    Walder, H.; Steiger, C.; Platzner, M.