Modeling gate current of nano scale MOSFET for circuit simulation

Modeling gate current of nano scale MOSFET for circuit simulation Purpose – The purpose of this paper is to develop analytical model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET with inevitable nano scale effects (NSE). Design/methodology/approach – A computationally efficient model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET in nano scale is presented. The model predictions are compared with the two‐dimensional Sentaurus device simulation. Findings – Good agreement between the model and experimental data was obtained. The model also shows good agreement when compared with Sentaurus simulation and available model. It is observed that neglecting NSE may lead to large error in the calculated gate tunneling current. The findings provide a guideline to the severity of NSE from the point of view of standby power consumption. It is found that temperature and substrate bias have almost negligible effect on gate tunneling current. The gate tunneling current variation with gate bias, gate oxide thickness and source/drain overlap region have also been assessed. Research limitations/implications – The present work is concentrated only on the gate leakage current and is useful for gate leakage analysis of the circuits. Practical implications – The model so developed is conceptually simple, numerically efficient and can be used for circuit simulator. Originality/value – NSE are considered while modeling the gate tunneling current through nano scale n‐channel MOSFET. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Multidiscipline Modeling in Materials and Structures Emerald Publishing

Modeling gate current of nano scale MOSFET for circuit simulation

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Publisher
Emerald Publishing
Copyright
Copyright © 2011 Emerald Group Publishing Limited. All rights reserved.
ISSN
1573-6105
DOI
10.1108/15736101111157073
Publisher site
See Article on Publisher Site

Abstract

Purpose – The purpose of this paper is to develop analytical model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET with inevitable nano scale effects (NSE). Design/methodology/approach – A computationally efficient model for gate tunneling current for an ultra‐thin gate oxide n‐channel MOSFET in nano scale is presented. The model predictions are compared with the two‐dimensional Sentaurus device simulation. Findings – Good agreement between the model and experimental data was obtained. The model also shows good agreement when compared with Sentaurus simulation and available model. It is observed that neglecting NSE may lead to large error in the calculated gate tunneling current. The findings provide a guideline to the severity of NSE from the point of view of standby power consumption. It is found that temperature and substrate bias have almost negligible effect on gate tunneling current. The gate tunneling current variation with gate bias, gate oxide thickness and source/drain overlap region have also been assessed. Research limitations/implications – The present work is concentrated only on the gate leakage current and is useful for gate leakage analysis of the circuits. Practical implications – The model so developed is conceptually simple, numerically efficient and can be used for circuit simulator. Originality/value – NSE are considered while modeling the gate tunneling current through nano scale n‐channel MOSFET.

Journal

Multidiscipline Modeling in Materials and StructuresEmerald Publishing

Published: Aug 9, 2011

Keywords: MOSFET; Gate tunnelling; Nano scale effects; Gate oxide thickness; Source/drain overlap region; Simulation; Modelling

References

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