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Finite element modeling to analyze durability of BGA/CSP connections during thermal shock

Finite element modeling to analyze durability of BGA/CSP connections during thermal shock Personal electronic devices at the user interface, like cell phones, utilize BGA/CSP structure for miniaturization of circuits. These structures are subjected to severe thermal loads due to environment of use. Starting with a microstructure of a failed board due to thermal cycles, the stresses/strains in this structure were analyzed from –408C to 1258C. In the finite element models (ABAQUS), we represented the structure as a composite of three‐dimensional (3‐D) elastic materials. The model showed stress/strain/energy concentrations at the actual failure points. The model also provided a route to improved durability by reducing these failure potentials, through change in the substrate of the printed circuit board (PCB). We observed significant reduction in failure potential when resin coated copper was replaced by THERMOUNT1 in PCB. This improved performance can be directly related to better‐matched modulus and coefficient of thermal expansion (CTE) of the PCB substrate to the chip (silicon). A more sophisticated model is under construction, where the time dependent material properties and non‐linear effects such as solder creep will be included. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Circuit World Emerald Publishing

Finite element modeling to analyze durability of BGA/CSP connections during thermal shock

Subhotosh Khan; Dan J. Molligan
Circuit World , Volume 27 (4): 5 – Dec 1, 2001
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Publisher
Emerald Publishing
Copyright
none
ISSN
0305-6120
DOI
10.1108/03056120110695777
Publisher site
See Article on Publisher Site

Abstract

Personal electronic devices at the user interface, like cell phones, utilize BGA/CSP structure for miniaturization of circuits. These structures are subjected to severe thermal loads due to environment of use. Starting with a microstructure of a failed board due to thermal cycles, the stresses/strains in this structure were analyzed from –408C to 1258C. In the finite element models (ABAQUS), we represented the structure as a composite of three‐dimensional (3‐D) elastic materials. The model showed stress/strain/energy concentrations at the actual failure points. The model also provided a route to improved durability by reducing these failure potentials, through change in the substrate of the printed circuit board (PCB). We observed significant reduction in failure potential when resin coated copper was replaced by THERMOUNT1 in PCB. This improved performance can be directly related to better‐matched modulus and coefficient of thermal expansion (CTE) of the PCB substrate to the chip (silicon). A more sophisticated model is under construction, where the time dependent material properties and non‐linear effects such as solder creep will be included.

Journal

Circuit World – Emerald Publishing

Published: Dec 1, 2001

Keywords: Finite element modelling; Durability; Ball grid array; Chip scale packaging; Thermal stress

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