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Exploiting narrow values for faster parity generation

Exploiting narrow values for faster parity generation Purpose – The purpose of this paper is to reduce parity generation latency if the input value is narrow. Design/methodology/approach – Soft errors caused by cosmic particles and radiation emitted by the packaging are important problems in contemporary microprocessors. Parity bits are used to detect single bit errors that occur in the storage components. In order to implement parity logic, multiple levels of XOR gates are used and these XOR trees are known to have high delay. Many produced and consumed values inside a processor hold consecutive zeros and ones in their upper order bits. These values can be represented with less number of bits and hence are termed narrow. In this paper, a parity generator circuit design is proposed that is capable of generating parity if the input value is narrow. It is shown that the parity can be generated faster than a regular XOR tree implementation using this design for the values that can be represented using fewer bits. Findings – The proposed technique reduces the parity generation latency of 64‐bit values by 50 percent for eight‐bit narrow values. Considering the fact that around 70 percent of the immediate values written to the immediate field of the issue queue and around 40 percent of the value written to the integer register file can be expressed with only eight bits, the coverage of the proposed scheme is quite high. Originality/value – This paper shows the simulation results of fast parity generator circuit if the input value is narrow. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Microelectronics International Emerald Publishing

Exploiting narrow values for faster parity generation

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Publisher
Emerald Publishing
Copyright
Copyright © 2009 Emerald Group Publishing Limited. All rights reserved.
ISSN
1356-5362
DOI
10.1108/13565360910981526
Publisher site
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Abstract

Purpose – The purpose of this paper is to reduce parity generation latency if the input value is narrow. Design/methodology/approach – Soft errors caused by cosmic particles and radiation emitted by the packaging are important problems in contemporary microprocessors. Parity bits are used to detect single bit errors that occur in the storage components. In order to implement parity logic, multiple levels of XOR gates are used and these XOR trees are known to have high delay. Many produced and consumed values inside a processor hold consecutive zeros and ones in their upper order bits. These values can be represented with less number of bits and hence are termed narrow. In this paper, a parity generator circuit design is proposed that is capable of generating parity if the input value is narrow. It is shown that the parity can be generated faster than a regular XOR tree implementation using this design for the values that can be represented using fewer bits. Findings – The proposed technique reduces the parity generation latency of 64‐bit values by 50 percent for eight‐bit narrow values. Considering the fact that around 70 percent of the immediate values written to the immediate field of the issue queue and around 40 percent of the value written to the integer register file can be expressed with only eight bits, the coverage of the proposed scheme is quite high. Originality/value – This paper shows the simulation results of fast parity generator circuit if the input value is narrow.

Journal

Microelectronics International – Emerald Publishing

Published: Jul 31, 2009

Keywords: Error analysis; Codes; Circuits

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