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Energy efficient IEEE 754 floating point multiplier using dual spacer delay insensitive logic

Energy efficient IEEE 754 floating point multiplier using dual spacer delay insensitive logic PurposeThe purpose of this paper is to present a single-precision floating-point multiplier where a low-power operation is attained through the reduction of switching activity. A floating-point multiplier is the basic building block for many applications such as digital signal processing (DSP) processors and multimedia applications involving a large dynamic range.Design/methodology/approachA floating-point multiplier was implemented in asynchronous logic such as multi-threshold null conventional logic and the proposed multi-threshold dual spacer dual rail delay insensitive logic (MTD3L). The proposed logic deals with high performance and energy efficiency.FindingsThe Institute of Electrical and Electronics Engineering (IEEE) has provided a standard to define the floating-point representation, which is known as the IEEE 754 standard. Rounding has not been implemented because it is not suitable for high-precision applications.Originality/valueThe performance aspects of the proposed asynchronous MTD3L floating-point multiplier are obtained using a Mentor Graphics tool and are compared with those of the existing asynchronous logic. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Circuit World Emerald Publishing

Energy efficient IEEE 754 floating point multiplier using dual spacer delay insensitive logic

Jyothula, Sudhakar; K., Sushma
Circuit World , Volume 43 (2): 8 – May 2, 2017
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References (5)

Publisher
Emerald Publishing
Copyright
Copyright © Emerald Group Publishing Limited
ISSN
0305-6120
DOI
10.1108/CW-03-2017-0012
Publisher site
See Article on Publisher Site

Abstract

PurposeThe purpose of this paper is to present a single-precision floating-point multiplier where a low-power operation is attained through the reduction of switching activity. A floating-point multiplier is the basic building block for many applications such as digital signal processing (DSP) processors and multimedia applications involving a large dynamic range.Design/methodology/approachA floating-point multiplier was implemented in asynchronous logic such as multi-threshold null conventional logic and the proposed multi-threshold dual spacer dual rail delay insensitive logic (MTD3L). The proposed logic deals with high performance and energy efficiency.FindingsThe Institute of Electrical and Electronics Engineering (IEEE) has provided a standard to define the floating-point representation, which is known as the IEEE 754 standard. Rounding has not been implemented because it is not suitable for high-precision applications.Originality/valueThe performance aspects of the proposed asynchronous MTD3L floating-point multiplier are obtained using a Mentor Graphics tool and are compared with those of the existing asynchronous logic.

Journal

Circuit World – Emerald Publishing

Published: May 2, 2017

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