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Edge detection using resistive threshold logic networks with CMOS flash memories

Edge detection using resistive threshold logic networks with CMOS flash memories Purpose – The purpose of this paper is to present a new approach to edge detection using semiconductor flash memory networks having scalable and parallel hardware architecture. Design/methodology/approach – A flash cell can store multiple states by controlling its voltage threshold. The equivalent resistance of the operation states controlled by threshold voltage of flash cell gives out different combinations of logic 0 and 1 states. The paper explores this basic feature of flash memory in designing a resistance change memory network for implementing novel edge detector hardware. This approach of detecting the edges is inspired from the spatial change detection ability of the human visual system. Findings – The proposed approach consumes less number of electronic components for its implementation, and outperforms the conventional approaches of edge detection with respect to the processing speed, scalability and ease of design. It is also demonstrated to provide edges invariant to changes in the direction of the spatial change in the images. Research limitations/implications – This research brings about a new direction in the development of edge detection, in terms of developing high‐speed parallel processing edge detection and imaging circuits. Practical implications – The proposed approach reduces the implementation complexity by removing the need to have convolution operations for spatial edge filtering. Originality/value – This paper presents one of the first edge detection approaches that is purely a hardware oriented design, uses resistance of flash memory to form edge detector cells, and one that does not use computational operations such as additions or multiplications for its implementation. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png International Journal of Intelligent Computing and Cybernetics Emerald Publishing

Edge detection using resistive threshold logic networks with CMOS flash memories

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Publisher
Emerald Publishing
Copyright
Copyright © 2014 Emerald Group Publishing Limited. All rights reserved.
ISSN
1756-378X
DOI
10.1108/IJICC-06-2013-0032
Publisher site
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Abstract

Purpose – The purpose of this paper is to present a new approach to edge detection using semiconductor flash memory networks having scalable and parallel hardware architecture. Design/methodology/approach – A flash cell can store multiple states by controlling its voltage threshold. The equivalent resistance of the operation states controlled by threshold voltage of flash cell gives out different combinations of logic 0 and 1 states. The paper explores this basic feature of flash memory in designing a resistance change memory network for implementing novel edge detector hardware. This approach of detecting the edges is inspired from the spatial change detection ability of the human visual system. Findings – The proposed approach consumes less number of electronic components for its implementation, and outperforms the conventional approaches of edge detection with respect to the processing speed, scalability and ease of design. It is also demonstrated to provide edges invariant to changes in the direction of the spatial change in the images. Research limitations/implications – This research brings about a new direction in the development of edge detection, in terms of developing high‐speed parallel processing edge detection and imaging circuits. Practical implications – The proposed approach reduces the implementation complexity by removing the need to have convolution operations for spatial edge filtering. Originality/value – This paper presents one of the first edge detection approaches that is purely a hardware oriented design, uses resistance of flash memory to form edge detector cells, and one that does not use computational operations such as additions or multiplications for its implementation.

Journal

International Journal of Intelligent Computing and Cybernetics – Emerald Publishing

Published: Mar 4, 2014

Keywords: Image processing; Cognitive systems; Evolvable hardware

References

  • Introduction to flash memory
    Bez, R.; Camerlenghi, E.; Modelli, A.; Visconti, A.
  • CUDA Application Design and Development
    Farber, R.
  • Flash memory scaling
    Fazio, A.
  • MSP430 flash memory characteristics
    Forstner, P.
  • A new simple method for extracting the capacitance coupling coefficients of sub‐0.5‐micrometer flash memory cells
    Haraguchi, K.; Kume, H.; Ushiyama, M.; Ohkura, M.
  • Cognitive memory network
    James, A.; Dimitrijev, S.
  • Resistive threshold logic
    James, A.P.; Francis, L.R.V.; Kumar, D.S.
  • A simple flash memory cell model for transient circuit simulation
    Kang, Y.H.; Hong, S.
  • GPU implementation of a deformable 3D image registration algorithm
    Mousazadeh, H.; Marami, B.; Sirouspour, S.; Patriciu, A.
  • NVCR: a transparent checkpoint‐restart library for NVIDIA CUDA
    Nukada, A.; Takizawa, H.; Matsuoka, S.
  • Low‐cost, high‐speed computer vision using NVIDIAs CUDA architecture
    Park, S.I.; Ponce, S.; Huang, J.; Cao, Y.; Quek, F.
  • The effect of negative VTH of NAND flash memory cells on data retention characteristics
    Park, M.; Ahn, E.; Cho, E.; Kim, K.; Lee W.S.
  • Flash memory cells: an overview
    Pavan, P.; Bez, R.; Olivo, P.; Zanoni, E.
  • CUDA by Example: An Introduction to General‐Purpose GPU Programming
    Sanders, J.; Kandrot, E.
  • A variable threshold voltage inverter for CMOS programmable logic circuits
    Segura, J.; Rossello, J.L.; Morra, J.; Sigg, H.
  • Independent‐gate FinFET circuit design methodology
    Wang, M.C.
  • GPU accelerated fuzzy connected image segmentation by using CUDA
    Zhuge, Y.; Cao, Y.; Miller, R.W.