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Design, integration and implementation of crypto cores in an SoC environment

Design, integration and implementation of crypto cores in an SoC environment The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.Design/methodology/approachAn integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.FindingsFPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.Originality/valueThe proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Microelectronics International Emerald Publishing

Design, integration and implementation of crypto cores in an SoC environment

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Publisher
Emerald Publishing
Copyright
© Emerald Publishing Limited
ISSN
1356-5362
eISSN
1356-5362
DOI
10.1108/mi-09-2021-0091
Publisher site
See Article on Publisher Site

Abstract

The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.Design/methodology/approachAn integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.FindingsFPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.Originality/valueThe proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

Journal

Microelectronics International – Emerald Publishing

Published: May 17, 2022

Keywords: Hardware architecture; Ciphers; AES; PRESENT; VLSI architecture; ASIC; FPGA–SoC

References

  • Area efficient-high throughput sub-pipelined design of the AES in CMOS 180nm
    Alma’Aitah, A.; Abid, Z.-E.
  • An evaluation of AES and PRESENT ciphers for lightweight cryptography on smartphones
    Andrés, C.; Miguel, M.; Arturo, D.
  • PRESENT: an ultra-lightweight block cipher
    Bogdanov, A.; Knudsen, L.R.; Leander, G.; Paar, C.; Poschmann, A.; Robshaw, M.J.; Seurin, Y.; Vikkelsoe, C.
  • A high-throughput cost-effective ASIC implementation of the AES algorithm
    Cao, Q.; Li, S.
  • CAST: digital IP cores and subsystems
  • Evaluation of SPN-based lightweight crypto-ciphers
    Dalmasso, L.; Bruguier, F.; Benoit, P.; Torres, L.
  • A compact, low power AES core on 180nm CMOS process
    Dao, V.-L.; Hoang, V.-P.; Nguyen, A.-T.; Le, Q.-M.
  • Ac’97 soundmax codec
    Devices, A.
  • An open-source VHDL IP library with plug&play configuration
    Gaisler, J.; Jacquart, R.
  • GRLIB IP library user’s manual
    Gaisler, J.; Catovic, E.
  • Energy and performance evaluation of an FPGA-based SoC platform with AES and PRESENT coprocessors
    Guo, X.; Chen, Z.; Schaumont, P.
  • AES: current security and efficiency analysis of its alternatives
    Isa, H.; Bahari, I.; Sufian, H.; Z’aba, M.R.
  • GIFT cipher usage in image data security: hardware implementations, performance and statistical analyses
    Jangir, A.; Pandey, J.G.
  • Securing the internet of things: a standardization perspective
    Keoh, S.L.; Kumar, S.S.; Tschofenig, H.
  • Towards green cryptography: a comparison of lightweight ciphers from the energy viewpoint
    Kerckhof, S.; Durvaux, F.; Hocquet, C.; Bol, D.; Standaert, F.-X.
  • A 2.3 gb/s fully integrated and synthesizable AES rijndael core
    Kim, N.S.; Mudge, T.; Brown, R.
  • Architectural optimization for a 1.82 gbits/sec VLSI implementation of the AES rijndael algorithm
    Kuo, H.; Verbauwhede, I.
  • An evaluation of AES and PRESENT ciphers for lightweight cryptography on smartphones
    Lara-Nino, C.A.; Morales-Sandoval, M.; Diaz-Perez, A.
  • Novel FPGA-based low-cost hardware architecture for the PRESENT block cipher
    Lara-Nino, C.A.; Morales-Sandoval, M.; Diaz-Perez, A.
  • High-throughput low-area design of AES using constant binary matrix-vector multiplication
    Lee, H.; Paik, Y.; Jun, J.; Han, Y.; Kim, S.W.
  • Efficient and flexible architecture for AES
    Li, H.
  • Lorawan overview
  • A highly regular and scalable AES hardware architecture
    Mangard, S.; Aigner, M.; Dominikus, S.
  • A high-performance and area-efficient VLSI architecture for the PRESENT lightweight cipher
    Pandey, J.G.; Goel, T.; Karmakar, A.
  • A high-performance VLSI architecture of the PRESENT cipher and its implementations for SoCs
    Pandey, J.G.; Goel, T.; Nayak, M.; Mitharwal, C.; Karmakar, A.; Singh, R.
  • A unified architecture for AES/PRESENT ciphers and its usage in an SoC environment
    Pandey, J.G.; Gupta, S.; Karmakar, A.
  • 197: advanced encryption standard (AES)
    Pub, N.F.
  • Ultra-lightweight implementations for smart devices–security for 1000 gate equivalents
    Rolfes, C.; Poschmann, A.; Leander, G.; Paar, C.
  • A side-channel leakage free coprocessor IC in 0.18 μm CMOS for embedded AES-based cryptographic and biometric processing
    Tiri, K.; Hwang, D.; Hodjat, A.; Lai, B.; Yang, S.; Schaumont, P.; Verbauwhede, I.
  • A low area, low power 8-bit AES-CCM authenticated encryption core in 180nm CMOS process
    Van Lan, D.; Thai, N.A.; Van Phuc, H.
  • Design and performance testing of a 2.29-gb/s rijndael processor
    Verbauwhede, I.; Schaumont, P.; Kuo, H.
  • An energy-efficient crypto-extension design for RISC-V
    Wang, W.; Han, J.; Cheng, X.; Zeng, X.
  • Ml505/ml506/ml507 evaluation platform
  • Implementation approaches for the advanced encryption standard algorithm
    Zhang, X.; Parhi, K.K.
  • High-speed VLSI architectures for the AES algorithm
    Zhang, X.; Parhi, K.K.
  • Software design specification z-wave device class specification document no.sds10242
  • PDK of 180 nm technology