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References (21)
-
L. Coulibaly, H. Kadim (2005)
Analytical delay computation for arbitrary distributed RLC treesInternational Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005., 2
-
K. Agarwal, D. Sylvester, D. Blaauw (2006)
Modeling and analysis of crosstalk noise in coupled RLC interconnectsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25
-
H. Kawaguchi, T. Sakurai (1998)
Delay and noise formulas for capacitively coupled distributed RC linesProceedings of 1998 Asia and South Pacific Design Automation Conference
-
R. Venkatesan, Jeffrey Davis, J. Meindl (2003)
Compact distributed RLC interconnect models - part IV: unified models for time delay, crosstalk, and repeater insertionIEEE Transactions on Electron Devices, 50
-
Sourajeet Roy, A. Dounavis (2009)
Closed-Form Delay and Crosstalk Models for $RLC$ On-Chip Interconnects Using a Matrix Rational ApproximationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28
-
Guoqing Chen, E. Friedman (2005)
An RLC interconnect model based on fourier analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24
-
T. Sakurai (1983)
Approximation of wiring delay in MOSFET LSIIEEE Journal of Solid-State Circuits, 18
-
R. Venkatesan, Jeffrey Davis, J. Meindl (2003)
Compact distributed RLC interconnect models - part III: transients in single and coupled lines with capacitive load terminationIEEE Transactions on Electron Devices, 50
-
L. Pileggi, R. Rohrer (1990)
Asymptotic waveform evaluation for timing analysisIEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9
-
Jeffrey Davis, J. Meindl (2000)
Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networksIEEE Transactions on Electron Devices, 47
-
Y. Ismail, E. Friedman, J. Neves (1999)
Equivalent Elmore delay for RLC treesProceedings 1999 Design Automation Conference (Cat. No. 99CH36361)
-
A. Kahng, S. Muddu, E. Sarto (2000)
On switch factor based analysis of coupled RC interconnectsProceedings 37th Design Automation Conference
-
10.1109/43.664231
-
10.1109/43.822622
-
Semiconductor Industry Association
International Technology Roadmap for Semiconductors -
T. Sakurai (1993)
Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIsIEEE Transactions on Electron Devices, 40
-
A. Kahng, S. Muddu (1996)
An analytical delay model for RLC interconnects1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96, 4
-
B. Kaushik, S. Sarkar, R. Agarwal, R. Joshi (2006)
Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnectsMicroelectronics International, 23
-
Frank Liu, Chandramouli Kashyap, C. Alpert (2002)
A delay metric for RC circuits based on the Weibull distributionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23
-
B. Kaushik, S. Sarkar (2008)
Crosstalk Analysis for a CMOS-Gate-Driven Coupled InterconnectsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27
-
J. Rabaey (1995)
Digital Integrated Circuits: A Design Perspective
- Publisher
- Emerald Publishing
- Copyright
- Copyright © 2014 Emerald Group Publishing Limited. All rights reserved.
- ISSN
- 1726-0531
- DOI
- 10.1108/JEDT-08-2013-0056
- Publisher site
- See Article on Publisher Site
Abstract
Purpose – The purpose of this paper is to propose an analytical model for estimating propagation delay in coupled resistance‐inductance‐capacitance (RLC) interconnects. Design/methodology/approach – With higher frequency of operation, longer length of interconnect and fast transition time of the signal, the resistor capacitor (RC) models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are required. In this paper, an analytical model for estimation of interconnect delay is developed for simultaneously switching lines. Two distributed RLC lines coupled inductively and capacitively are considered. To validate the proposed model, SPICE results are compared with the proposed analytical results. Each line in the coupled structure is terminated by a capacitive load of 30fF. The driving signal is considered symmetrical with equal rise and fall time of 5 ps and OFF/ON time of 45 ps. The model is validated for both in‐phase and out of phase switching of lines. Findings – It is observed that the model works well for both the phases of inputs switching. The derived expressions of delay exhibit complete physical insight, and the results obtained are in excellent agreement with SPICE results. Comparison of analytical delay with SPICE delay shows an average error of < 2.7 per cent. Originality/value – The analytical expressions for interconnect delay are derived for the first time under simultaneously switching scenario. This model is useful to estimate delay across the inductively and capacitively coupled interconnects.
Journal
Journal of Engineering Design and Technology – Emerald Publishing
Published: Jul 1, 2014
Keywords: Coupled interconnects; Delay; Analytical model; Lossy transmission lines; Simultaneous switching.