Delay model for dynamically switching coupled on‐chip interconnects

Delay model for dynamically switching coupled on‐chip interconnects Purpose – The purpose of this paper is to propose an analytical model for estimating propagation delay in coupled resistance‐inductance‐capacitance (RLC) interconnects. Design/methodology/approach – With higher frequency of operation, longer length of interconnect and fast transition time of the signal, the resistor capacitor (RC) models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are required. In this paper, an analytical model for estimation of interconnect delay is developed for simultaneously switching lines. Two distributed RLC lines coupled inductively and capacitively are considered. To validate the proposed model, SPICE results are compared with the proposed analytical results. Each line in the coupled structure is terminated by a capacitive load of 30fF. The driving signal is considered symmetrical with equal rise and fall time of 5 ps and OFF/ON time of 45 ps. The model is validated for both in‐phase and out of phase switching of lines. Findings – It is observed that the model works well for both the phases of inputs switching. The derived expressions of delay exhibit complete physical insight, and the results obtained are in excellent agreement with SPICE results. Comparison of analytical delay with SPICE delay shows an average error of < 2.7 per cent. Originality/value – The analytical expressions for interconnect delay are derived for the first time under simultaneously switching scenario. This model is useful to estimate delay across the inductively and capacitively coupled interconnects. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Journal of Engineering, Design and Technology Emerald Publishing

Delay model for dynamically switching coupled on‐chip interconnects

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Publisher
Emerald Publishing
Copyright
Copyright © 2014 Emerald Group Publishing Limited. All rights reserved.
ISSN
1726-0531
DOI
10.1108/JEDT-08-2013-0056
Publisher site
See Article on Publisher Site

Abstract

Purpose – The purpose of this paper is to propose an analytical model for estimating propagation delay in coupled resistance‐inductance‐capacitance (RLC) interconnects. Design/methodology/approach – With higher frequency of operation, longer length of interconnect and fast transition time of the signal, the resistor capacitor (RC) models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are required. In this paper, an analytical model for estimation of interconnect delay is developed for simultaneously switching lines. Two distributed RLC lines coupled inductively and capacitively are considered. To validate the proposed model, SPICE results are compared with the proposed analytical results. Each line in the coupled structure is terminated by a capacitive load of 30fF. The driving signal is considered symmetrical with equal rise and fall time of 5 ps and OFF/ON time of 45 ps. The model is validated for both in‐phase and out of phase switching of lines. Findings – It is observed that the model works well for both the phases of inputs switching. The derived expressions of delay exhibit complete physical insight, and the results obtained are in excellent agreement with SPICE results. Comparison of analytical delay with SPICE delay shows an average error of < 2.7 per cent. Originality/value – The analytical expressions for interconnect delay are derived for the first time under simultaneously switching scenario. This model is useful to estimate delay across the inductively and capacitively coupled interconnects.

Journal

Journal of Engineering, Design and TechnologyEmerald Publishing

Published: Jul 1, 2014

Keywords: Coupled interconnects; Delay; Analytical model; Lossy transmission lines; Simultaneous switching.

References

  • Equivalent Elmore delay for RLC trees
    Ismail, Y.I.; Friedman, E.G.; Neves, J.L.
  • On switch factor based analysis of coupled RC interconnects
    Kahng, A.B.; Muddu, S.; Sarto, S.
  • A delay metric for RC circuits based on the weibull distribution
    Liu, F.; Kashyap, C.; Alpert, C.J.
  • Asymptotic waveform evaluation for timing analysis
    Pillage, L.T.; Rohrer, R.A.

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