Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards Purpose – This paper aims to address the various issues of board‐level (off‐chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off‐chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted. Design/methodology/approach – The problems in board‐level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board‐level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique. Findings – The dominant‐1 (wired‐OR, denoted as WOR), dominant‐0 (wired‐AND, denoted as WAND) and stuck‐at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms. Research limitations/implications – The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults. Practical implications – The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors. Originality/value – Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board‐level dominant‐1 (WOR), dominant‐0 (WAND) and stuck‐at faults. The proposed algorithm is completely free from aliasing and confounding syndromes. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Circuit World Emerald Publishing

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Circuit World, Volume 37 (3): 8 – Aug 23, 2011

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Publisher
Emerald Publishing
Copyright
Copyright © 2011 Emerald Group Publishing Limited. All rights reserved.
ISSN
0305-6120
DOI
10.1108/03056121111155648
Publisher site
See Article on Publisher Site

Abstract

Purpose – This paper aims to address the various issues of board‐level (off‐chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off‐chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted. Design/methodology/approach – The problems in board‐level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board‐level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique. Findings – The dominant‐1 (wired‐OR, denoted as WOR), dominant‐0 (wired‐AND, denoted as WAND) and stuck‐at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms. Research limitations/implications – The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults. Practical implications – The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors. Originality/value – Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board‐level dominant‐1 (WOR), dominant‐0 (WAND) and stuck‐at faults. The proposed algorithm is completely free from aliasing and confounding syndromes.

Journal

Circuit WorldEmerald Publishing

Published: Aug 23, 2011

Keywords: Boundary scan; BIST; TPG; Off‐chip interconnects; Faults; Electrical testing; Electronic engineering

References

  • Reconfigurable tester hardware extends JTAG/boundary scan applications while simplifying ATE setup
    Ehrenberg, H.
  • Research on design for testability of PCB based on JTAG
    Hui, J.; Xutao, C.
  • Built in self test: early development and future trends
    Mucha, J.
  • Use of JTAG boundary scan for testing electronics circuit boards and system
    Ngo, B.V.; Law, P.; Spark, P.
  • VLSI interconnects and their testing – prospects and challenges ahead
    Sharma, D.K.; Kaushik, B.K.; Sharma, R.K.

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