Get 20M+ Full-Text Papers For Less Than $1.50/day. Start a 14-Day Trial for You or Your Team.

Learn More →

A multilayer process for the connection of fine‐pitch‐devices on molded interconnect devices (MIDs)

A multilayer process for the connection of fine‐pitch‐devices on molded interconnect devices (MIDs) Purpose – The purpose of this paper is to present a new multilayer process for three‐dimensional molded interconnect devices (3D‐MIDs) that allows the assembly of modern area array packaged semiconductors. Design/methodology/approach – A new 3D‐MID multilayer process based on local overmolding is developed. To investigate this new process, a 3D demonstrator is designed, simulated and fabricated. Various technologies such as injection molding, maskless laser assisted electroless metallization, overmolding and laser via drilling are used. Findings – Using the new 3D‐MID multilayer process a 3D demonstrator with three metallization layers is fabricated. Injection molding simulation is utilized to ensure a feasible demonstrator design. It is shown that a surface laser treatment improves layer‐to‐layer adhesion during the process. Shear and pull tests prove the adhesion promotion. The 3D fine‐pitch‐metallization is done down to 60 μ m track width. Via resistance is measured by four terminal sensing in agreement with previous results. Design rules for process compatible vias are introduced. The fabricated demonstrator is suitable for flip‐chip‐based area array packaged semiconductors. Research limitations/implications – A proof of concept is given by the fabricated demonstrator. Further, work should include reliability tests of the multilayer structures and improvement of individual process steps. Originality/value – The paper describes a new multilayer process for 3D‐MIDs. It overcomes existing restrictions regarding the electrical routing on 3D‐MID surfaces. The compatibility of area array packaged semiconductors with a high‐inputs/outputs count and the 3D‐MID technology is improved. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Circuit World Emerald Publishing

A multilayer process for the connection of fine‐pitch‐devices on molded interconnect devices (MIDs)

Circuit World , Volume 35 (2): 7 – May 15, 2009

Loading next page...
 
/lp/emerald-publishing/a-multilayer-process-for-the-connection-of-fine-pitch-devices-on-QtS5RAzJkl

References (19)

Publisher
Emerald Publishing
Copyright
Copyright © 2009 Emerald Group Publishing Limited. All rights reserved.
ISSN
0305-6120
DOI
10.1108/03056120910953286
Publisher site
See Article on Publisher Site

Abstract

Purpose – The purpose of this paper is to present a new multilayer process for three‐dimensional molded interconnect devices (3D‐MIDs) that allows the assembly of modern area array packaged semiconductors. Design/methodology/approach – A new 3D‐MID multilayer process based on local overmolding is developed. To investigate this new process, a 3D demonstrator is designed, simulated and fabricated. Various technologies such as injection molding, maskless laser assisted electroless metallization, overmolding and laser via drilling are used. Findings – Using the new 3D‐MID multilayer process a 3D demonstrator with three metallization layers is fabricated. Injection molding simulation is utilized to ensure a feasible demonstrator design. It is shown that a surface laser treatment improves layer‐to‐layer adhesion during the process. Shear and pull tests prove the adhesion promotion. The 3D fine‐pitch‐metallization is done down to 60 μ m track width. Via resistance is measured by four terminal sensing in agreement with previous results. Design rules for process compatible vias are introduced. The fabricated demonstrator is suitable for flip‐chip‐based area array packaged semiconductors. Research limitations/implications – A proof of concept is given by the fabricated demonstrator. Further, work should include reliability tests of the multilayer structures and improvement of individual process steps. Originality/value – The paper describes a new multilayer process for 3D‐MIDs. It overcomes existing restrictions regarding the electrical routing on 3D‐MID surfaces. The compatibility of area array packaged semiconductors with a high‐inputs/outputs count and the 3D‐MID technology is improved.

Journal

Circuit WorldEmerald Publishing

Published: May 15, 2009

Keywords: Semiconductor technology; Metallization; Adhesion

There are no references for this article.