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3D Si‐on‐Si stack packaging

3D Si‐on‐Si stack packaging A new concept of 3D‐electronic packaging is presented: Si‐on‐Si multi‐chip module flip‐chip technology with arrays of fine etched and filled vertical electrical interconnections (vias). Arrays of vias with a high number of interconnections, and not only peripheral interconnections are used. A 3D Si‐on‐Si stack package demonstrator has been realized consisting of four Si‐substrates each representing a system level and containing four thinned and flip‐chip assembled chips. The chips are flip‐chip mounted on the flat side of the Si‐substrates. When interconnecting the Si‐substrates by bump technology the chips submerge into cavities on the rear side of the adjacent Si‐substrate. The chips also test the technology and quality of the electronic packaging, and therefore contain a set of thin film heaters, junctions for temperature measuring, Al‐meanders for stress and strain measuring and daisy chains for conduction path monitoring. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Soldering & Surface Mount Technology Emerald Publishing

3D Si‐on‐Si stack packaging

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References (7)

Publisher
Emerald Publishing
Copyright
Copyright © 2000 MCB UP Ltd. All rights reserved.
ISSN
0954-0911
DOI
10.1108/09540910010312429
Publisher site
See Article on Publisher Site

Abstract

A new concept of 3D‐electronic packaging is presented: Si‐on‐Si multi‐chip module flip‐chip technology with arrays of fine etched and filled vertical electrical interconnections (vias). Arrays of vias with a high number of interconnections, and not only peripheral interconnections are used. A 3D Si‐on‐Si stack package demonstrator has been realized consisting of four Si‐substrates each representing a system level and containing four thinned and flip‐chip assembled chips. The chips are flip‐chip mounted on the flat side of the Si‐substrates. When interconnecting the Si‐substrates by bump technology the chips submerge into cavities on the rear side of the adjacent Si‐substrate. The chips also test the technology and quality of the electronic packaging, and therefore contain a set of thin film heaters, junctions for temperature measuring, Al‐meanders for stress and strain measuring and daisy chains for conduction path monitoring.

Journal

Soldering & Surface Mount Technology – Emerald Publishing

Published: Apr 1, 2000

Keywords: Fault analysis; Electronic packing; Multi‐chip module; Flip chip

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