Self-aligned gate-last process for quantum-well InAs transistor on insulator

Self-aligned gate-last process for quantum-well InAs transistor on insulator This paper presents a promising technology to make quantum-well InAs transistors on SiO2/Si substrate by using a self-aligned gate-last fabrication technique. The full self-aligned fabrication process is demonstrated, and the fabricated device is characterized. A 2-D TCAD simulation is then performed based on the experimental data to understand the operation of the InAs transistors. We explore further optimizations for this technology through TCAD simulations, and it is found that with optimizations in materials, device geometry and fabrication, significant boost in RF performances is possible with these devices. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Microelectronic Engineering Elsevier

Self-aligned gate-last process for quantum-well InAs transistor on insulator

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Publisher
Elsevier
Copyright
Copyright © 2018 Elsevier Ltd
ISSN
0167-9317
eISSN
1873-5568
D.O.I.
10.1016/j.mee.2018.01.030
Publisher site
See Article on Publisher Site

Abstract

This paper presents a promising technology to make quantum-well InAs transistors on SiO2/Si substrate by using a self-aligned gate-last fabrication technique. The full self-aligned fabrication process is demonstrated, and the fabricated device is characterized. A 2-D TCAD simulation is then performed based on the experimental data to understand the operation of the InAs transistors. We explore further optimizations for this technology through TCAD simulations, and it is found that with optimizations in materials, device geometry and fabrication, significant boost in RF performances is possible with these devices.

Journal

Microelectronic EngineeringElsevier

Published: May 5, 2018

References

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