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On testing cache-coherent shared memories

On testing cache-coherent shared memories On Testing Phil.lip AT&T Murray gibbons@ Cache-Coherent B. Gibbons Shared Ephraim Ben- Gurion Memories Korach University Bell Laboratories Hill NJ 07974 att. con 600 Mount ain Avenue research. of the Negev Beer- Sheva 84105, Israel korach@bgumail .bgu. ac. il Abstract Sequential consistency is the most-widely used correctness condition for multiprocessor memory systems. High-performance shared memory multiprocessors such as the Kendall Square KSR1, the Stanford DASH, and the MIT Alewife employ a variety of techniques to improve memory system performance while providing sequential consistency. Primary among them is the use of caches at each processor, kept coherent by protocols implemented in hardware. We study the problem of testing shared memory multiprocessors to determine if they are indeed providing a sequentially consistent memory. We present a series of results for testing an execution of a shared memory under scenarios that exploit the cache-coherence protocol. In addition to reads and writes to the shared memory, we consider the more powerful read-modify-write, load-reserved, and store-conditional operations available in many cachecoherent multiprocessors. Finally, we consider linearizabllity, another well-known correctness condition for shared memories. LinearizabiKty imposes additional restrictions on the shared memory, beyond that of sequential consistency; we show that these restrictions are useful http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

On testing cache-coherent shared memories

Gibbons, Phillip B.; Korach, Ephraim
Association for Computing Machinery — Aug 1, 1994
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Datasource
Association for Computing Machinery
Copyright
Copyright © 1994 by ACM Inc.
ISBN
0-89791-671-9
doi
10.1145/181014.181328
Publisher site
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Abstract

On Testing Phil.lip AT&T Murray gibbons@ Cache-Coherent B. Gibbons Shared Ephraim Ben- Gurion Memories Korach University Bell Laboratories Hill NJ 07974 att. con 600 Mount ain Avenue research. of the Negev Beer- Sheva 84105, Israel korach@bgumail .bgu. ac. il Abstract Sequential consistency is the most-widely used correctness condition for multiprocessor memory systems. High-performance shared memory multiprocessors such as the Kendall Square KSR1, the Stanford DASH, and the MIT Alewife employ a variety of techniques to improve memory system performance while providing sequential consistency. Primary among them is the use of caches at each processor, kept coherent by protocols implemented in hardware. We study the problem of testing shared memory multiprocessors to determine if they are indeed providing a sequentially consistent memory. We present a series of results for testing an execution of a shared memory under scenarios that exploit the cache-coherence protocol. In addition to reads and writes to the shared memory, we consider the more powerful read-modify-write, load-reserved, and store-conditional operations available in many cachecoherent multiprocessors. Finally, we consider linearizabllity, another well-known correctness condition for shared memories. LinearizabiKty imposes additional restrictions on the shared memory, beyond that of sequential consistency; we show that these restrictions are useful

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