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The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model

The design of Viterbi decoder for low power consumption space time trellis code without adder... <jats:sec> <jats:title content-type="abstract-subheading">Purpose</jats:title> <jats:p>This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD).</jats:p> </jats:sec> <jats:sec> <jats:title content-type="abstract-subheading">Design/methodology/approach</jats:title> <jats:p>The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm.</jats:p> </jats:sec> <jats:sec> <jats:title content-type="abstract-subheading">Findings</jats:title> <jats:p>The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps.</jats:p> </jats:sec> <jats:sec> <jats:title content-type="abstract-subheading">Originality/value</jats:title> <jats:p>It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review.</jats:p> </jats:sec> http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png World Journal of Engineering CrossRef

The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model

World Journal of Engineering , Volume 13 (6): 540-546 – Dec 5, 2016

The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model


Abstract

<jats:sec>
<jats:title content-type="abstract-subheading">Purpose</jats:title>
<jats:p>This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD).</jats:p>
</jats:sec>
<jats:sec>
<jats:title content-type="abstract-subheading">Design/methodology/approach</jats:title>
<jats:p>The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm.</jats:p>
</jats:sec>
<jats:sec>
<jats:title content-type="abstract-subheading">Findings</jats:title>
<jats:p>The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps.</jats:p>
</jats:sec>
<jats:sec>
<jats:title content-type="abstract-subheading">Originality/value</jats:title>
<jats:p>It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review.</jats:p>
</jats:sec>

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References (13)

Publisher
CrossRef
ISSN
1708-5284
DOI
10.1108/wje-09-2016-0088
Publisher site
See Article on Publisher Site

Abstract

<jats:sec> <jats:title content-type="abstract-subheading">Purpose</jats:title> <jats:p>This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD).</jats:p> </jats:sec> <jats:sec> <jats:title content-type="abstract-subheading">Design/methodology/approach</jats:title> <jats:p>The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm.</jats:p> </jats:sec> <jats:sec> <jats:title content-type="abstract-subheading">Findings</jats:title> <jats:p>The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps.</jats:p> </jats:sec> <jats:sec> <jats:title content-type="abstract-subheading">Originality/value</jats:title> <jats:p>It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review.</jats:p> </jats:sec>

Journal

World Journal of EngineeringCrossRef

Published: Dec 5, 2016

There are no references for this article.