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Storage assignment optimizations through variable coalescence for embedded processors

Storage assignment optimizations through variable coalescence for embedded processors Modern embedded processors with dedicated address generation unit support memory access with indirect addressing mode with auto-increment and decrement. The auto-increment/decrement mode saves address arithmetic instructions.Liao et al 23 categorized this problem as simple offset assignment (SOA) problem and general offset assignment (GOA) problem, which involve storage layout of variables and assignment of address registers respectively proposing heuristic solutions. Later work 67 proposed improvements in the performance of Liao's solution by undertaking program and storage transformations that affect access sequence.The algorithms are incorporated into and evaluated on the commercial compiler provided by Motorola to boost code generation performance on the DSP 56k chip. Compared to previous approaches, variable coalescence with program reordering reduces SOA costs by 48% and GOA (2AR) costs by 66% for Mediabench and SPEC benchmarks. Moreover, we show that our approach obtains theoretically optimal solution (zero cost) for the GOA problem in 87% of the cases with just 2 address registers and in 94% of the cases with 3 address registers. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM SIGPLAN Notices Association for Computing Machinery

Storage assignment optimizations through variable coalescence for embedded processors

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2003 by ACM Inc.
ISSN
0362-1340
DOI
10.1145/780731.780763
Publisher site
See Article on Publisher Site

Abstract

Modern embedded processors with dedicated address generation unit support memory access with indirect addressing mode with auto-increment and decrement. The auto-increment/decrement mode saves address arithmetic instructions.Liao et al 23 categorized this problem as simple offset assignment (SOA) problem and general offset assignment (GOA) problem, which involve storage layout of variables and assignment of address registers respectively proposing heuristic solutions. Later work 67 proposed improvements in the performance of Liao's solution by undertaking program and storage transformations that affect access sequence.The algorithms are incorporated into and evaluated on the commercial compiler provided by Motorola to boost code generation performance on the DSP 56k chip. Compared to previous approaches, variable coalescence with program reordering reduces SOA costs by 48% and GOA (2AR) costs by 66% for Mediabench and SPEC benchmarks. Moreover, we show that our approach obtains theoretically optimal solution (zero cost) for the GOA problem in 87% of the cases with just 2 address registers and in 94% of the cases with 3 address registers.

Journal

ACM SIGPLAN NoticesAssociation for Computing Machinery

Published: Jul 11, 2003

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