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F ault S im : A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems

F ault S im : A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked... FAULTSIM: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems PRASHANT J. NAIR, School of Electrical and Computer Engineering, Georgia Institute of Technology DAVID A. ROBERTS, AMD Research, Advanced Micro Devices Inc. MOINUDDIN K. QURESHI, School of Electrical and Computer Engineering, Georgia Institute of Technology As memory systems scale, maintaining their Reliability Availability and Serviceability (RAS) is becoming more complex. To make matters worse, recent studies of DRAM failures in data centers and supercomputer environments have highlighted that large-granularity failures are common in DRAM chips. Furthermore, the move toward 3D-stacked memories can make the system vulnerable to newer failure modes, such as those occurring from faults in Through-Silicon Vias (TSVs). To architect future systems and to use emerging technology, system designers will need to employ strong error correction and repair techniques. Unfortunately, evaluating the relative effectiveness of these reliability mechanisms is often difficult and is traditionally done with analytical models, which are both error prone and time-consuming to develop. To this end, this article proposes FAULTSIM, a fast configurable memory-reliability simulation tool for 2D and 3D-stacked memory systems. FaultSim employs Monte Carlo simulations, which are driven by real-world failure statistics. We discuss the novel algorithms and data http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Architecture and Code Optimization (TACO) Association for Computing Machinery

F ault S im : A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2015 by ACM Inc.
ISSN
1544-3566
DOI
10.1145/2831234
Publisher site
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Abstract

FAULTSIM: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems PRASHANT J. NAIR, School of Electrical and Computer Engineering, Georgia Institute of Technology DAVID A. ROBERTS, AMD Research, Advanced Micro Devices Inc. MOINUDDIN K. QURESHI, School of Electrical and Computer Engineering, Georgia Institute of Technology As memory systems scale, maintaining their Reliability Availability and Serviceability (RAS) is becoming more complex. To make matters worse, recent studies of DRAM failures in data centers and supercomputer environments have highlighted that large-granularity failures are common in DRAM chips. Furthermore, the move toward 3D-stacked memories can make the system vulnerable to newer failure modes, such as those occurring from faults in Through-Silicon Vias (TSVs). To architect future systems and to use emerging technology, system designers will need to employ strong error correction and repair techniques. Unfortunately, evaluating the relative effectiveness of these reliability mechanisms is often difficult and is traditionally done with analytical models, which are both error prone and time-consuming to develop. To this end, this article proposes FAULTSIM, a fast configurable memory-reliability simulation tool for 2D and 3D-stacked memory systems. FaultSim employs Monte Carlo simulations, which are driven by real-world failure statistics. We discuss the novel algorithms and data

Journal

ACM Transactions on Architecture and Code Optimization (TACO) – Association for Computing Machinery

Published: Dec 8, 2015

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