TY - JOUR
AU - Jun'an, Zhang
AB - A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 m CMOS process and achieves an SNR of 82 dB.
TI - A 16-bit cascaded sigma-delta pipeline A/D converter
JO - Journal of Semiconductors
DO - 10.1088/1674-4926/30/5/055010
DA - 2009-05-01
UR - https://www.deepdyve.com/lp/iop-publishing/a-16-bit-cascaded-sigma-delta-pipeline-a-d-converter-yYaGMrcLbP
SP - 055010
VL - 30
IS - 5
DP - DeepDyve
ER -