TY - JOUR
AU - Zhang, Feng
AB - This paper demonstrates the design and implementation of a 5-GHz frequency synthesizer using 55-nm complementary metal-oxide semiconductor technology. The proposed synthesizer achieves an ultra-low 0.35-ps jitter with a high-resolution adaptive frequency calibration scheme that automatically chooses frequency-tuning curves and improves calibration accuracy. The proposed synthesizer employs a high-Q LC voltage-controlled oscillator, constant bandwidth, low, and even 
$$K_{\mathrm{VCO}}$$



K
VCO



 technique using thermometer-weighted capacitor calibration, a low-power divider, and a charge-pump (CP) circuit to achieve low jitter. The oscillator comprises a modified digitally controlled capacitor and varactor array, which extend the tuning range and minimize the phase noise. A matched differential CP is adopted to reduce reference spurs and phase-noise performance. The proposed frequency synthesizer achieves an output frequency of 4.4–5.6 GHz with a chip area of 
$$0.33\hbox { mm}^{2}$$



0.33


mm
2




. The power consumption is 20 mW from a 1.2-V supply at 5 GHz, and the reference spur is −67.99 dBc. The measured root mean-square random jitter and phase noise are 0.35 ps and −110.04 dBc/Hz at 1 MHz, respectively.
TI - Design of 0.35-ps RMS Jitter 4.4–5.6-GHz Frequency Synthesizer with Adaptive Frequency Calibration Using 55-nm CMOS Technology
JF - Circuits, Systems and Signal Processing
DO - 10.1007/s00034-017-0645-z
DA - 2017-09-01
UR - https://www.deepdyve.com/lp/springer-journals/design-of-0-35-ps-rms-jitter-4-4-5-6-ghz-frequency-synthesizer-with-yMuGPacz4Q
SP - 1479
EP - 1504
VL - 37
IS - 4
DP - DeepDyve
ER -