TY - JOUR
AU - Pozniak, Krzysztof T.
AB - The article discusses a method of building a universal, parameterized clock management module for the process of functional simulation. The solution was designed for various families of FPGA circuits and popular VHDL compilers. The algorithm for automatic module configuration for given parameters of output clocks and method of synchronization with the reference clock are discussed. The basic solution implemented in the VHDL language in a behavioral form and selected examples of practical use for complex clock signal relations are presented in detail.
TI - VHDL-based parameterized clock manager simulator for FPGA
JF - Proceedings of SPIE
DO - 10.1117/12.2501465
DA - 2018-10-01
UR - https://www.deepdyve.com/lp/spie/vhdl-based-parameterized-clock-manager-simulator-for-fpga-yMdKuK63a1
SP - 108083Y
EP - 108083Y-10
VL - 10808
IS - 
DP - DeepDyve
ER -