TY - JOUR
AU - Shin, Youngsoo
AB - The area required by combinational logic of a sequential circuit based on standard flip-flops can be reduced by identifying subcircuits that are identical. Pairs of matching subcircuits can then be replaced by circuits in which dual-edge-triggered flip-flops operate on multiplexed data at the rising and falling edges of the clock signal. We show how to modify the Boolean network describing a combinational logic to increase the opportunities for folding, without affecting its function. Experiments with benchmark circuits achieved an average reduction in circuit area of 18%.
TI - Folded Circuit Synthesis
JF - ACM Transactions on Design Automation of Electronic Systems (TODAES)
DO - 10.1145/3229082
DA - 2018-08-22
UR - https://www.deepdyve.com/lp/association-for-computing-machinery/folded-circuit-synthesis-vDbZYED9ts
SP - 1
EP - 21
VL - 23
IS - 5
DP - DeepDyve
ER -