TY - JOUR
AU - Lin, Ting-Ting
AB -  Optimization of Power Dissipation and Skew Sensitivity in Clock Buffer Synthesis Jae W. Chung , De-Yu Kao ¡, Chung-Kuan Cheng , and Ting-Ting Lin ¡ Department of Computer Science and Engineering Mail Code 0114 University of California, San Diego La Jolla, California 92093-0114 ¡ Department of Electrical and Computer Engineering Mail Code 0407 University of California, San Diego La Jolla, California 92093-0407 As we have noticed, no manufacturing parameters have been considered in these works. Thus, zero skew suffers from a considerable skew in practice. Also, all the previous works have been done under the assumption that a single clock source drives all the sinks distributed in the whole chip. As a result, excessive delays are introduced by the long interconnect wires between the clock source and the clock sinks. Recently Chung and Cheng [7] proposed a method of reducing the skew sensitivity and phase delay by inserting buffers. They considered wire width variations to achieve a reliable clock signal and proposed an ef cient algorithm by adopting a dynamic programming method in nding optimal buffer locations in the clock tree. Lin et al. [12] presented a process variation tolerant clock routing mechanism. Cong and Koh [5] proposed 
TI - Optimization of power dissipation and skew sensitivity in clock buffer synthesis
DA - 1995-04-23
UR - https://www.deepdyve.com/lp/association-for-computing-machinery/optimization-of-power-dissipation-and-skew-sensitivity-in-clock-buffer-txd0h9Wk5N
DP - DeepDyve
ER -