TY - JOUR
AU - Kakad, Yogendra P.
AB - An algorithm is developed in the companion paper, to update the existing DFT to represent the new data series that results when a new signal point is received. Updating the DFT in this way uses less computation than directly evaluating the DFT using the FFT algorithm, This reduces the computational order by a factor of log2 N. The algorithm is able to work in the presence of data window function, for use with rectangular window, the split triangular, Hanning, Hamming, and Blackman windows. In this paper, a hardware implementation of this algorithm, using FPGA technology, is outlined. Unlike traditional fully customized VLSI circuits, FPGAs represent a technical break through in the corresponding industry. The FPGA implements thousands of gates of logic in a single IC chip and it can be programmed by users at their site in a few seconds or less depending on the type of device used. The risk is low and the development time is short. The advantages have made FPGAs very popular for rapid prototyping of algorithms in the area of digital communication, digital signal processing, and image processing. Our paper addresses the related issues of implementation using hardware descriptive language in the development of the design and the subsequent downloading on the programmable hardware chip.
TI - Rapid prototyping of update algorithm of discrete Fourier transform for real-time signal processing
JF - Proceedings of SPIE
DO - 10.1117/12.445399
DA - 2001-10-22
UR - https://www.deepdyve.com/lp/spie/rapid-prototyping-of-update-algorithm-of-discrete-fourier-transform-svwWsd2ZF0
SP - 501
EP - 508
VL - 4379
IS - 1
DP - DeepDyve
ER -