TY - JOUR
AU - Men, B, Y
AB - Abstract An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes. acoustic logging, signal source, field programmable gate array (FPGA), delay, amplitude, frequency 1. Introduction Sonic logging tools mainly contain sonic emission systems, sonic receiving systems and signal processing systems (Ju et al2012; Lu et al2008). During research and field application, tools only do their jobs when these three parts are combined, thus they are easily affected by the factors of fields and environments. So, it is important to resolve questions such as the debugging of critical circuits in the process of researching, examining and repairing acoustic logging tools, the verification of corresponding algorithms of acoustic logging tools, and the finding of equipment failures. Some research studies have been carried out on logging imitation signal sources: Zhang et al (2000) have produced a sinusoidal synthesis waveform whose frequency could be adjusted by using a microprocessor and DDS synthesis technology. Hu (2008) has produced an FPGA-based sinusoidal waveform whose frequency and amplitude could be adjusted. Evans and Jenkins (1978) have produced a pulse waveform by using a microprocessor and phase-locked technology. All of these researchers have produced logging imitation signals using different methods, but all of them produced only one signal which was simple, fixed and had fewer modulation functions. This paper designs and realizes a four channel signal source which can imitate arbitrary waveforms received by acoustic receiving transducers. The signal source is provided with many adjustment functions, and these can be used to imitate influences on acoustic logging received waveforms caused by many kinds of factors such as spacings and spans of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes, etc. 1.1. Hardware design of the signal source Figure 1 illustrates the hardware design of the imitation signal source, which mainly consists of an FPGA control chip (Shi et al2012), a USB interface circuit, a trigger circuit, a parameter control circuit, four digital to analog conversion circuits, and four signal processing circuits. The main workflow of the signal source follows. Firstly, the FPGA begins to work under the control of the trigger circuit and receives all kinds of parameters from the parameter control circuit. Secondly, the FPGA reads the waveform’s simulation data inside of its RAM and outputs them to the digital to analog conversion circuit. Thirdly, it controls the digital to analog conversion circuit to convert digital signals into analog signals and controls the signal processing circuit to enlarge and smooth these analog signals. Lastly, it outputs the four channels’ logging imitation signals. Figure 1. Open in new tabDownload slide Hardware block diagram of imitation signal source. Figure 1. Open in new tabDownload slide Hardware block diagram of imitation signal source. The FPGA control chip is the control core of the whole signal source, its RAM can store data which can be used to store the waveform’s simulation data, and its multipliers can be used to carry out multiplication and division. The USB interface circuits mainly consist of a USB interface, an interface transformation chip (FT232), and its peripheral components. The FT232 can realize transformation between the USB interface and the Universal Asynchronous Receiver/Transmitter (UART) interface, and it can also be converted to a synchronous mode or an asynchronous Bit-Bang interface mode. This circuit is used to communicate between the FPGA and the computer, in other words, to download the waveform’s imitation data into the FPGA from a personal computer. Both the USB interface circuit and the JTAG can download simulation data and software. However, downloading by JTAG needs a special downloading circuit and software, while downloading by USB interface circuit needs a USB device driver, and applications based on the Windows platform. JTAG is suitable for R&D personnel, and a USB interface circuit is more suitable for common users now that the USB device driver and applications have been successfully completed. The trigger circuit is mainly composed of some high-speed (10 MBit/s) serial light-couplers (HCPL-0600) and input/output interfaces. High-speed light-couplers are used to separate signals between the signal source and other circuits, which can prevent possible interference and damage caused by the latter to the former. The trigger circuit possesses two kinds of operating modes: external trigger mode and internal trigger mode. The parameter control circuit is mainly composed of five 8421 dial switches. These switches are separately used to modulate the overall delay, delay between channels, frequency, overall amplitude, and amplitude attenuation between channels. The overall delay can be used to imitate the influences on the arrival time of sonic logging received waveforms caused by the spacing of acoustic tools, and the sonic speeds of different layers and fluids. The delay between channels can be used to imitate the influences on the arrival moment difference of different receiving transducers caused by their different directions and positions. The frequency adjustment can used to imitate the influences on the received waveforms’ frequency caused by the working frequency of the launch transducer. The overall amplitude adjustment can be used to imitate influences on the received waveforms’ amplitude caused by the different layers and cementation planes. The amplitude attenuation adjustment between channels can be used to imitate the influences on the received waveforms’ amplitude change caused by the different spacing of acoustic tools. The digital to analog conversion circuit is mainly composed of a Digital to Analog Converter (DAC) AD5541A. It is used to change the digital signals inside of the FPGA RAM to voltage waveform signals under the control of the FPGA. Fundamentally, the signal processing circuit contains smoothing circuits, stored program controlled attenuation circuits, and fixed attenuation circuits. 1.2. Software design of the signal source The signal source’s software design is under the direction of the top-down modular design concept and utilizes a method of diagram type program. Figure 2 summarizes the imitation signal source’s software design, which consists of one trigger module, one clock module, one delay module, one FT232 control module, one RAM module, one amplitude adjustment module, and four transformation modules. Figure 2. Open in new tabDownload slide Software block diagram of imitation signal source. Figure 2. Open in new tabDownload slide Software block diagram of imitation signal source. The trigger module determines the signal source’s operating mode and generates a pulse signal to control the start of the signal source working. The clock module brings out clocks of different frequencies needed by the working system. The delay module produces delay control signals for the four channels. The FT232 control module yields control signals to control the FPGA getting data from the computer and updating these data to its RAM. The RAM module begins to work under the control of the delay control signals. The amplitude adjustment module completes the overall amplitude adjustment, using a multiplier and divider inside the FPGA to carry out simulation data’s multiplication and division, and completes the amplitude adjustment between channels by creating ADG408 control signals. The transformation module contains a parallel connection/serial connection transformation module, and a digital to analog transformation module. The overall simulation of the software design is executed by Quartus8.0 software, and the result is represented in figure 3 (for the sake of simplicity, only the first channel and the second channel are analyzed), Where ‘clk_in’ is the clock inputted; ‘clk_work’ is the working clock made by the clock module; ‘amp’ are the amplitude control signals including overall amplitude adjustment, and amplitude adjustment between channels; ‘dly’ are the delay control signals including overall delay adjustment and delay adjustment between channels; ‘frq’ are the frequency control signals; ‘reset’ is the outside trigger signal; ‘en1’—‘en4’ are outputting control signals, and each channel does its job when the corresponding control signal is high; ‘ram_data’ are parallel data made by the RAM module and the amplitude adjustment module; ‘sclk’, ‘cs’, ‘ldac’ and ‘signal’ are control signals made by the digital to analog transformation module: ‘sclk’ is the AD5541A chip’s working clock whose frequency is 16 MHz; and ‘cs’ is the chip select signal, which is used to trigger the input of the serial data frame. The AD5541A chip works when this signal keeps low; ‘signal’ is the serial data read into the input register at the rising edge of ‘sclk’ separately, and it is produced by the parallel data/serial data transformation module; ‘ldac’ is the logic input, when it becomes low, the data inside the DAC register and serial register are upgraded synchronously, this amounts to say, one transformation process is done by the AD5541A chip and a voltage analog signal is outputted. Figure 3. Open in new tabDownload slide Software overall emulation result figure of an imitation signal source. Figure 3. Open in new tabDownload slide Software overall emulation result figure of an imitation signal source. 1.3. Testing and the outcome analyses After the software is successfully downloaded into the FPGA chip, two kinds of tests are executed: (1) the waveforms outputted before and after all kinds of adjustments are gathered and sketched contrastingly, and also spectrum analyses are performed on the waveforms outputted before and after frequency adjustment; (2) the outputted waveforms are gathered by the sonic receiving system, and also calculation and verification are done to the collected waveform data using corresponding algorithms. The original waveform of the imitation signal is shown in figure 4. We can find that the amplitude is about 2.4 V, which corresponds with the range of the DAC and is attenuated before being outputted. Figure 4. Open in new tabDownload slide Original waveform of imitation signal. Figure 4. Open in new tabDownload slide Original waveform of imitation signal. 2. Waveform comparison test before and after adjustment Different waveform signals are generated by adjusting these five switches. The results are represented in figures 5 to 10, where ‘trigger’ is the inside trigger signal. Also the Signal to Noise Ratio of output signals is measured and calculated, and the outcome is 71 dB. Figure 5. Open in new tabDownload slide Effect contrast figure of overall amplitude adjustment. Figure 5. Open in new tabDownload slide Effect contrast figure of overall amplitude adjustment. The effect contrast figures of amplitude adjustments are shown in figures 5 and 6, where CH1–CH4 are the four original waveforms, CH1_AllAmp–CH4_AllAmp are the four waveforms outputted after overall amplitude modulation, CH1_DifAmp–CH4_DifAmp are the four waveforms outputted after amplitude attenuation modulation between channels. We find that the outputs of the signal source last about 3 ms and their amplitude is mV-level, which corresponds with the durations and amplitudes of real sonic logging received waveforms. The peak–peak amplitudes of four original waveforms are about 500 mV and are halved to about 250 mV after the overall amplitude modulation. After the amplitude attenuation modulation between channels, the first channel’s peak–peak amplitude remains unchanged, the second channel is halved to about 250 mV, the third is attenuated to about 120 mV and the fourth is about 60 mV. Figure 6. Open in new tabDownload slide Effect contrast figure of amplitude attenuation adjustment between channels. Figure 6. Open in new tabDownload slide Effect contrast figure of amplitude attenuation adjustment between channels. The effect contrast figure of frequency adjustment is shown in figure 6, CH1_Frq–CH4_Frq are waveforms outputted after frequency modulation. It is shown that the frequencies of the four waveforms changed obviously. Spectrum analyses are also performed on these eight waveforms and their results are shown in figure 8. The dominant frequencies of the four waveforms are 6.70 kHz before adjustment and 7.93 kHz after adjustment. Figure 7. Open in new tabDownload slide Effect contrast figure of frequency adjustment. Figure 7. Open in new tabDownload slide Effect contrast figure of frequency adjustment. Figure 8. Open in new tabDownload slide Frequency analysis figure about the result of frequency adjustment. Figure 8. Open in new tabDownload slide Frequency analysis figure about the result of frequency adjustment. The effect contrast figures of delay adjustments are shown in figures 9 and 10, CH1_AllDly–CH4_AllDly are four waveforms outputted after the overall delay adjustment, CH1_DifDly–CH4_DifDly are four waveforms outputted after the delay adjustment between channels. It is illustrated in these experiments that the arrival moment of the waveforms outputted after the overall delay is slightly later than the original waveforms, which is about 72 µs. After the delay adjustment between channels, the arrival moment of the second channel is 72 µs later than the first channel and the third channel is 72 µs later than the second, and so forth. Figure 9. Open in new tabDownload slide Effect contrast figure of overall delay adjustment. Figure 9. Open in new tabDownload slide Effect contrast figure of overall delay adjustment. Figure 10. Open in new tabDownload slide Effect contrast figure of delay adjustment between channels. Figure 10. Open in new tabDownload slide Effect contrast figure of delay adjustment between channels. 3. United test For the purposes of synchronous verification, the outputted waveforms of the signal source are gathered by the sonic signal receiving and processing system of our laboratory (Cheng et al 2012), and also calculation and verification are done to these collected waveform data using corresponding algorithms. The data are presented in table 1, where dominant frequencies are obtained by spectrum analyses of the received data. An enlargement of 12 dB has been executed for all waveforms while being received. The processes of all kinds of adjustment are as previously mentioned. The calculation of the delay and correlation coefficients are based on the values of the first channel’s original waveform. Table 1 shows that the results of synchronous verification are in complete accord with adjustment processes of the signal source, and signals between different channels have good consistency; thus, it is proved that the signal source, the sonic signal receiving and processing system, and these corresponding algorithms are all working well. Table 1. Result table of united test. Adjustment methods . Peak–peak amplitudes / V . Dominant frequencies / kHz . Delay / μs . Correlation coefficient . Original waveform of channel 4 1.76 6.71 0 1 Original waveform of channel 4 1.79 6.71 0 0.92 Original waveform of channel 4 1.76 6.71 0 0.93 Original waveform of channel 4 1.86 6.71 0 0.89 Overall amplitude of channel 1 0.99 6.71 0 — Overall amplitude of channel 2 0.93 6.71 0 — Overall amplitude of channel 3 0.96 6.71 0 — Overall amplitude of channel 4 0.93 6.71 0 — Amplitude between channels of channel 1 1.76 6.71 0 0.91 Amplitude between channels of channel 2 0.93 6.71 0 — Amplitude between channels of channel 3 0.54 6.71 0 — Amplitude between channels of channel 4 0.35 6.71 0 — Frequency of channel 1 1.76 7.93 0 — Frequency of channel 2 1.82 7.93 0 — Frequency of channel 3 1.76 7.93 0 — Frequency of channel 4 1.79 7.93 1 — Overall delay of channel 1 1.76 6.71 72 0.90 Overall delay of channel 2 1.70 6.71 72 0.85 Overall delay of channel 3 1.66 6.71 73 0.82 Overall delay of channel 4 1.66 6.71 73 0.82 Delay between channels of channel 1 1.76 6.71 0 0.93 Delay between channels of channel 2 1.63 6.71 73 0.78 Delay between channels of channel 3 1.60 6.71 145 0.80 Delay between channels of channel 4 1.64 6.71 217 0.81 Adjustment methods . Peak–peak amplitudes / V . Dominant frequencies / kHz . Delay / μs . Correlation coefficient . Original waveform of channel 4 1.76 6.71 0 1 Original waveform of channel 4 1.79 6.71 0 0.92 Original waveform of channel 4 1.76 6.71 0 0.93 Original waveform of channel 4 1.86 6.71 0 0.89 Overall amplitude of channel 1 0.99 6.71 0 — Overall amplitude of channel 2 0.93 6.71 0 — Overall amplitude of channel 3 0.96 6.71 0 — Overall amplitude of channel 4 0.93 6.71 0 — Amplitude between channels of channel 1 1.76 6.71 0 0.91 Amplitude between channels of channel 2 0.93 6.71 0 — Amplitude between channels of channel 3 0.54 6.71 0 — Amplitude between channels of channel 4 0.35 6.71 0 — Frequency of channel 1 1.76 7.93 0 — Frequency of channel 2 1.82 7.93 0 — Frequency of channel 3 1.76 7.93 0 — Frequency of channel 4 1.79 7.93 1 — Overall delay of channel 1 1.76 6.71 72 0.90 Overall delay of channel 2 1.70 6.71 72 0.85 Overall delay of channel 3 1.66 6.71 73 0.82 Overall delay of channel 4 1.66 6.71 73 0.82 Delay between channels of channel 1 1.76 6.71 0 0.93 Delay between channels of channel 2 1.63 6.71 73 0.78 Delay between channels of channel 3 1.60 6.71 145 0.80 Delay between channels of channel 4 1.64 6.71 217 0.81 Open in new tab Table 1. Result table of united test. Adjustment methods . Peak–peak amplitudes / V . Dominant frequencies / kHz . Delay / μs . Correlation coefficient . Original waveform of channel 4 1.76 6.71 0 1 Original waveform of channel 4 1.79 6.71 0 0.92 Original waveform of channel 4 1.76 6.71 0 0.93 Original waveform of channel 4 1.86 6.71 0 0.89 Overall amplitude of channel 1 0.99 6.71 0 — Overall amplitude of channel 2 0.93 6.71 0 — Overall amplitude of channel 3 0.96 6.71 0 — Overall amplitude of channel 4 0.93 6.71 0 — Amplitude between channels of channel 1 1.76 6.71 0 0.91 Amplitude between channels of channel 2 0.93 6.71 0 — Amplitude between channels of channel 3 0.54 6.71 0 — Amplitude between channels of channel 4 0.35 6.71 0 — Frequency of channel 1 1.76 7.93 0 — Frequency of channel 2 1.82 7.93 0 — Frequency of channel 3 1.76 7.93 0 — Frequency of channel 4 1.79 7.93 1 — Overall delay of channel 1 1.76 6.71 72 0.90 Overall delay of channel 2 1.70 6.71 72 0.85 Overall delay of channel 3 1.66 6.71 73 0.82 Overall delay of channel 4 1.66 6.71 73 0.82 Delay between channels of channel 1 1.76 6.71 0 0.93 Delay between channels of channel 2 1.63 6.71 73 0.78 Delay between channels of channel 3 1.60 6.71 145 0.80 Delay between channels of channel 4 1.64 6.71 217 0.81 Adjustment methods . Peak–peak amplitudes / V . Dominant frequencies / kHz . Delay / μs . Correlation coefficient . Original waveform of channel 4 1.76 6.71 0 1 Original waveform of channel 4 1.79 6.71 0 0.92 Original waveform of channel 4 1.76 6.71 0 0.93 Original waveform of channel 4 1.86 6.71 0 0.89 Overall amplitude of channel 1 0.99 6.71 0 — Overall amplitude of channel 2 0.93 6.71 0 — Overall amplitude of channel 3 0.96 6.71 0 — Overall amplitude of channel 4 0.93 6.71 0 — Amplitude between channels of channel 1 1.76 6.71 0 0.91 Amplitude between channels of channel 2 0.93 6.71 0 — Amplitude between channels of channel 3 0.54 6.71 0 — Amplitude between channels of channel 4 0.35 6.71 0 — Frequency of channel 1 1.76 7.93 0 — Frequency of channel 2 1.82 7.93 0 — Frequency of channel 3 1.76 7.93 0 — Frequency of channel 4 1.79 7.93 1 — Overall delay of channel 1 1.76 6.71 72 0.90 Overall delay of channel 2 1.70 6.71 72 0.85 Overall delay of channel 3 1.66 6.71 73 0.82 Overall delay of channel 4 1.66 6.71 73 0.82 Delay between channels of channel 1 1.76 6.71 0 0.93 Delay between channels of channel 2 1.63 6.71 73 0.78 Delay between channels of channel 3 1.60 6.71 145 0.80 Delay between channels of channel 4 1.64 6.71 217 0.81 Open in new tab 4. Conclusions This paper designs and realizes a kind of FPGA-based four channel acoustic logging imitation signal source. The signal source is provided with a system of adjustments and can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors, such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuation of different cementation planes. Acknowledgment This research was financially supported by National Natural Science Foundation of China (4087409, 11134011, 11204380) and National Science and Technology Major Project (2011ZX05020-009). The authors would like to thank Dr Xiaolong Hao at China University of Petroleum, Beijing, for his help in the test. References Hu K S . , 2008 Design of reference signal source for well logging based on FPGA , WORLD SCI-TECH R&D (Chinese) , vol. 30 (pg. 275 - 277 ) OpenURL Placeholder Text WorldCat Ju X D , Qiao W X , Zhao H L , Lu J Q , Men B Y , Wu W H . , 2012 System design of a new acoustic logging tool , WELL LOGGING TECHOLOGY (Chinese) , vol. 36 (pg. 507 - 510 ) OpenURL Placeholder Text WorldCat Lu J Q , Ju X D , Cheng X Y . , 2008 Design of cross-dipole array acoustic logging tool , J. Univ. Petrol. China (Chinese) , vol. 32 (pg. 42 - 46 ) OpenURL Placeholder Text WorldCat Shi Y B , Guo J , Cui N . , 2012 High precision digital frequency signal source based on FPGA 2012 International Conference on Solid State Devices and Materials Science ShangHai: China April (pg. 1342 - 1347 ) Evans W A , Jenkins R W . , 1978 A microprocessor-controlled phase-locked signal source , Microelectron. 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TI - Design of acoustic logging signal source of imitation based on field programmable gate array
JF - Journal of Geophysics and Engineering
DO - 10.1088/1742-2132/11/4/045008
DA - 2014-08-01
UR - https://www.deepdyve.com/lp/oxford-university-press/design-of-acoustic-logging-signal-source-of-imitation-based-on-field-q02yt7WIio
VL - 11
IS - 4
DP - DeepDyve
ER -