TY - JOUR
AB - International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064 Index Copernicus Value (2013): 6.14 | Impact Factor (2015): 6.391 Design and Analysis of Low Power High Speed Hybrid Alternative Full Adder Circuits 1 2 Shreedevi , Taranath H. B VTU Belgaum, M.tech in VLSI Design and Embedded System, Mangalore Institute of Technology and Engineering, Moodabidri. Mangalore, Karnataka, India Assistant Professor. Department of ECE, Mangalore Institute of Technology and Engineering, Moodabidri. Mangalore, Karnataka, India Abstract: These This project deals designs of 1-bit hybrid alternative full adder using complementary metal-oxide-semiconductor (CMOS) logic, gate diffusion input (GDI) technique, modified GDI and transmission gate logic are reported. These designs are implemented using Mentor graphics tool. Performance parameters such as power dissipation and transistor counts are comp ared with other designs and the existing designs such as complementary pass-transistor logic, transmission gate adder and hybrid pass-logic with static CMOS output drive full adder, transmission function adder, mixed topology of GDI with both inverter and mirror so on. This design is divided into three modules and found to working efficiently with less power dissipation and transistor count at 180 nm technology. Keywords: CMOS, hybrid adder, GDI full adder, low power, transistor count and adders 
TI - Design and Analysis of Low Power High Speed Hybrid Alternative Full Adder Circuits
JO - International Journal of Science and Research (IJSR)
DO - 10.21275/v5i5.nov163491
DA - 2015-05-05
UR - https://www.deepdyve.com/lp/unpaywall/design-and-analysis-of-low-power-high-speed-hybrid-alternative-full-ood3OWHqoq
DP - DeepDyve
ER -