TY - JOUR
AU - 
AB - High Power Supply Rejection LDO Regulator for Switching Applications Daniel Arbet, Martin Kova ´c, ˇ David Maljar, Luka ´s ˇ Nagy and Viera Stopjakova ´ Department of IC Design and Test, Institute of Electronics and Photonics, Slovak University of Technology, Bratislava, Slovakia e-mail: daniel.arbet@stuba.sk Abstract—The paper describes design and analysis of a MHz. Therefore, the value of PSR at high frequencies (above Low-Dropout Regulator (LDO) with a high value of the power 10 MHz) is the most important requirement determining the supply rejection (PSR) at high frequencies (above 10MHz). The LDO topology selection. proposed LDO was designed in a standard 65 nm CMOS For the reasons described above, it is important to focus technology. The output of the designed LDO can be adjusted by on development of LDO topologies that are able to suppress the voltage reference used in the LDO. The obtained results prove a very good PSR parameter at frequencies above 10 MHz, where the high-frequency switching noise. In this paper, we focused the value of -40 dB is observed in the worst case. Additionally, on the design and verification of a fully on-chip LDO with a the designed LDO topology exhibits promising load regulation high value 
TI - High Power Supply Rejection LDO Regulator for Switching Applications
JF - 2022 45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO)
DO - 10.23919/mipro55190.2022.9803648
DA - 2022-05-23
UR - https://www.deepdyve.com/lp/unpaywall/high-power-supply-rejection-ldo-regulator-for-switching-applications-j10cLIiiS0
DP - DeepDyve
ER -