TY - JOUR
AU - Park, Inhag
AB - A new architecture of field programmable gate array for high‐speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a onetime, two‐terminal programmable, very low‐impedance anti‐fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip‐flops, and arithmetic functions such as one‐bit full adder and two‐bit comparator. A novel programming architecture is designed for supplying large current through the anti‐fuse element, which drops the on‐resistance of anti‐fuse below 20 Ω. The chip has been fabricated using a 0.8‐μm n‐well complementary metal oxide semiconductor technology with two layers of metalization.
TI - A New Field Programmable Gate Array: Architecture and Implementation
JF - Etri Journal
DO - 10.4218/etrij.95.0195.0023
DA - 1995-07-01
UR - https://www.deepdyve.com/lp/wiley/a-new-field-programmable-gate-array-architecture-and-implementation-iUMSUsOrNY
SP - 21
EP - 30
VL - 17
IS - 2
DP - DeepDyve
ER -