TY - JOUR
AU - Akhter, Shamim
AB - Advancement of system-on-chip (SOC) design technologies has sparked a significant interest in intellectual property core (IP core) reuse among very large scale integration (VLSI) circuit designers. Reusing IP cores can save tedious work and significantly speed up the semiconductor development. The acquisition and utilization of IP Cores is appreciably replacing HDL modules for designing arithmetic circuits. Prefix adders are the most efficient circuits for binary addition which is a crucial functionality of arithmetic circuits in any processor. The parallel prefix adder (PPA) family of prefix adders is a descendant of the widely used carry look-ahead adders. In the proposed work, Sklansky PPA has been constructed utilizing user-defined i.e. custom IP cores for a wide range of input vector length. These custom IP cores have been synthesized using VIVADO tool targeting (xc7z020clg484-1) field programmable gate array (FPGA) device from Zynq family. The methodology adopted in the proposed work can be applied to construct PPA structures with any topologies.
TI - IP-Based Design and Analysis of Parallel Prefix Adder for FPGAs
JF - National Academy Science Letters
DO - 10.1007/s40009-024-01536-8
DA - 2024-11-28
UR - https://www.deepdyve.com/lp/springer-journals/ip-based-design-and-analysis-of-parallel-prefix-adder-for-fpgas-hIMmL2e2zL
SP - 1
EP - 5
VL - OnlineFirst
IS - 
DP - DeepDyve
ER -