TY - JOUR
AU - Tamitani, Ichiro
AB - This report describe the hardware architecture and software implementation of a hologram computing system developed at the MIT Media Laboratory. The hologram computing employs specialized stream-processing hardware embedded in the Cheops Image Processing system--a compact, block data-flow parallel processor. A superposition stream processor performs weighted summations of arbitrary 1D basis functions. A two-step holographic computation method--called Hogel-Vector encoding--utilizes the stream processor's computational power. An array of encoded hogel vectors, generated from a 3D scene description, is rapidly decoded using the processor. The resulting 36-megabyte holographic pattern is transferred to frame- buffers and then fed to a real-time electro-holographic display, producing 3D holographic images. System performance is sufficient to generate an image volume approximately 100 mm per side in 3 seconds. The architecture is scalable over a limited range in both display size and computational power. The limitations on system scalability will be identified and solutions proposed.
TI - Hardware architecture for rapid generation of electro-holographic fringe patterns
JF - Proceedings of SPIE
DO - 10.1117/12.206216
DA - 1995-04-12
UR - https://www.deepdyve.com/lp/spie/hardware-architecture-for-rapid-generation-of-electro-holographic-dXlVzMS2Ia
SP - 172
EP - 183
VL - 2406
IS - 1
DP - DeepDyve
ER -