TY - JOUR
AU - Hanuman, C. R. S.
AB - Magnetic Tunnel Junction (MTJ) is an important device to store the non-volatile. This MTJ device overcomes the disadvantages of CMOS technology by reducing the leakage power. Also, it stores the data in magnet domain. Non Volatile combinational circuits are nonvolatile memory elements, which distributes over a logic-circuit plane and expected to realize both the ultra-low-power and reduced interconnection delay. The existing Spin Orbit Torque- Magnetic Tunnel Junction method is used to store data with higher density, cost benefits, endurance and Non-Volatility. But it has some limitations, such as high current density needed for writing can infrequently damage the MTJ barrier, achieving reliable reading without making a difference remains a challenge. More constraints limit the designer to attain higher speed with reliable MRAM architectures, because the operations of writing and reading share the same path (via the junction). To overcome these limitations, an innovative nonvolatile combinational circuit depending on Spin Transfer Torque (STT) with perpendicular Magnetic Tunnel Junction (STT-PMTJ) is proposed in this manuscript for fast data storage in real time applications. Here, the nonvolatile combinational circuits are Spin Transfer Torque and Spin Orbit Torque. The proposed method gives higher reliability and the lower resistive writing path acts high-speed with energy-efficient WRITE operation with the help of Read and Write Parallel Switching (RWPS). The RWPS circuit is designed using Spin Orbit Torque (SOT) logic. The RWPS-PMTJ device used to maximize the robustness of entire structure and the noise is apparently reduced. The performance of the proposed method is compared with other existing methods, such as STT-MTJ, SOT-MRAM. The experimental results shows that the proposed RWPS-PMTJ method is efficiently reduced write delay by 64% compared to the STT switching, it also exhibits 61% faster read access with full swing eventually eliminating the setup time requirement. It enables the design of a new era of In-memory computing circuits to meet the challenges in the design of memory-based computation logic circuits. The AND logic gate and Full Adder (FA) circuits are implemented using Cadence virtuoso 45 nm technology.
TI - A novel expeditious switching circuit design for non volatile combinational circuit
JF - Analog Integrated Circuits and Signal Processing
DO - 10.1007/s10470-022-02086-z
DA - 2022-12-01
UR - https://www.deepdyve.com/lp/springer-journals/a-novel-expeditious-switching-circuit-design-for-non-volatile-SfHTLua0WP
SP - 331
EP - 342
VL - 113
IS - 3
DP - DeepDyve
ER -