TY - JOUR
AU - Saneei, Mohsen
AB - In this paper, a low‐power and high‐resolution latch‐based time‐to‐digital converter (TDC) based on a multistage scheme is proposed. The proposed multistage TDC includes coarse, middle, and fine stages. The coarse stage is a new design of the flash TDC that is implemented by latches without using the delay cell. Also, the middle stage is a new design of the Vernier TDC with employed latches. The fine stage comprises parallel latches with different input loads.
TI - Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology
JO - International Journal of Circuit Theory and Applications
DO - 10.1002/cta.2468
DA - 2018-01-01
UR - https://www.deepdyve.com/lp/wiley/low-power-latch-based-multistage-time-to-digital-converter-in-65-nm-Rz0eOE3E2R
SP - 1264
EP - 1271
VL - 46
IS - 6
DP - DeepDyve
ER -