TY - JOUR
AU - Warr, Paul
AB - Within integrated circuit design, parasitic capacitance associated with the realisation of a resistor can limit circuit performance for certain applications, such as the analogue-to-digital converter. In this paper, a segmentation guarding layout technique is introduced that offers the circumvention of the parasitic capacitance of integrated resistors. The segmentation guarding technique is demonstrated on both diffusion and polysilicon integrated resistors.
TI - A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors
JF - Analog Integrated Circuits and Signal Processing
DO - 10.1007/s10470-017-0982-7
DA - 2017-04-22
UR - https://www.deepdyve.com/lp/springer-journals/a-segmentation-layout-guarding-technique-to-mitigate-parasitic-PGGjkypTey
SP - 237
EP - 243
VL - 93
IS - 2
DP - DeepDyve
ER -