TY - JOUR
AU - Lee, George
AB - This paper presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) designed using a 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 1.9–7.8 GHz. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and a two stage acquisition process to obtain the fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented which includes a coarse acquisition stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage to achieve resolution of 18.75 kHz for phase tracking. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a peak-to-peak jitter value of <15 ps and a root mean square jitter value of 4 ps when locked at 5.12 GHz. The power consumption at 7.8 GHz is 8 mW and the frequency hopping time is 3.5 μs for a 3.2 GHz frequency change. Spectre simulations demonstrate ADPLL convergence to 5.12 GHz for the typical, fast, and slow process corners to support robust performance considering process variations.
TI - Design of high-frequency wide-range all digital phase locked loop in 90nm CMOS
JF - Analog Integrated Circuits and Signal Processing
DO - 10.1007/s10470-013-0043-9
DA - 2013-02-16
UR - https://www.deepdyve.com/lp/springer-journals/design-of-high-frequency-wide-range-all-digital-phase-locked-loop-in-O2TlluJ3Jm
SP - 133
EP - 145
VL - 75
IS - 1
DP - DeepDyve
ER -