TY - JOUR
AU1 - Lin, Cheng-I
AU2 - Lee, Ko-Hui
AU3 - Lin, Horng-Chih
AU4 - Huang, Tiao-Yuan
AB - In this work, we have successfully demonstrated the feasibility of a method, which relies solely on I-line-based lithography, for fabricating sub-100 nm tri-gated junctionless (JL) poly-Si nanowire (NW) transistors. This method employs sidewall spacer etching and photoresist (PR) trimming techniques to shrink the channel length and width, respectively. With this approach, channel length and width down to 90 and 93 nm, respectively, are achieved in this work. The fabricated devices exhibit superior device characteristics with low subthreshold swing of 285 mV/dec and on/off current ratio larger than 107.
TI - Fabrication of tri-gated junctionless poly-Si transistors with I-line based lithography
JF - Japanese Journal of Applied Physics
DO - 10.7567/JJAP.53.04EA01
DA - 2014-01-01
UR - https://www.deepdyve.com/lp/iop-publishing/fabrication-of-tri-gated-junctionless-poly-si-transistors-with-i-line-Mq5tpROj0j
SP - 04EA01
VL - 53
IS - 4S
DP - DeepDyve
ER -