TY - JOUR
AU - Jamal, K.
AB - Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are linked to further enhance overall nerve amplification capacity. Large volumes of multicast on-chip or cross-chip can further complicate the construction of a cross-link network and create a NN barrier of device capacity and resources. In this paper, this refer to inter-chip and inter-chip communication strategies known as neuron connection for NN accelerators. Interconnect for powerful fault-tolerant routing system neural NoC is implemented in this paper. This recommends crossbar arbitration placement, virtual interrupts, and path-based parallelization strategies in terms of intra-chip communications for the virtual channel routing resulting in higher NoC output at lower hardware costs. A lightweight NoC compatible chip-to-chip interconnection scheme is proposed regarding to inter-chip communication for multicast-based data traffic to enable efficient interconnection for NoC-based NN chips. Moreover, the proposed methods will be tested with four Field Programmable Gate Arrays (FPGAs) on four hard-wired deep neural network (DNN) chips. From the experimental results it can be illustrate that a high throguput can obtained effectively by the proposed interconnection network in handling thedata traffic and low DNN through advanced links.
TI - An Efficient Interconnection System for Neural NOC Using Fault Tolerant Routing Method
JO - Journal of Physics: Conference Series
DO - 10.1088/1742-6596/2089/1/012069
DA - 2021-11-01
UR - https://www.deepdyve.com/lp/iop-publishing/an-efficient-interconnection-system-for-neural-noc-using-fault-Kk8PhZrigl
VL - 2089
IS - 1
DP - DeepDyve
ER -