TY - JOUR
AU - Rahim, N. A.
AB - 1. Introduction In response to the escalating global energy demand, the use of renewable energy is expanding day by day. Due to its reliability and environmentally friendly nature, governments and policymakers have also prioritized the development of new technologies to address energy needs. Although renewable energy systems like photovoltaic (PV), wind, and fuel cells (FC), etc. have gained significant momentum [1–4], the main obstacle to their growth consists in the low power conversion efficiency. On one hand, the output voltage of both the PV module and fuel cell is very low and the PV power output is directly affected by the diurnal changes in solar intensity. Consequently, a higher-voltage step-up dc-dc converter is necessary to amplify the output and ensure compatibility with other devices or applications [5, 6]. Furthermore, there is a demand for greater voltage-gain dc-dc converters in other applications, in addition to the domains described before. Several instances include offshore wind energy [3], electric, hybrid electric or fuel-cell vehicles [7–9], power systems integrating both medium- and high-voltage DC (MVDC and HVDC) [10, 11], and various other applications relying on fuel cells [12]. High step-up dc-dc converters can be categorized based on their active switches, isolation state, level of efficiency, voltage-gain technique, etc. [13–15]. Each group has some pros and cons. In recent times, a lot of research has been carried out to build non-isolated (transformer-less) topologies to attain high gain [16–18]. These are easier to build with a higher power density (in the absence of a transformer), cost-effective, and simple operation. They are appropriate for applications where electrical isolation is not a primary concern and lower power applications. Several new research has been performed using high turns ratio transformers to make a high-gain converter for renewable power [19–21]. On the other hand, isolated boost converters with transformers have several merits including the provision of electrical isolation between the input and output, resolving ground loop problems and safety issues, suitable for high-power applications, and improving voltage regulation and less electromagnetic interference (EMI). These characteristics enable their integration into high-power systems with enhanced stability and robust control. Nevertheless, they encounter several challenges, including increased size due to additional isolation components, higher cost, winding losses, elevated leakage inductance, and reduced efficiency as pointed out in [22]. These issues have been tackled by using more active switches for active clamping and some expensive and complicated control methods [23–25]. The PWM dc–dc converters have the most basic isolated designs, which include the Forward, the Flyback, the Push–Pull (PP), and the conventional Ćuk, Sepic, and Zeta with galvanic isolation. However, their static dc voltage step-up ratio isn’t as good as it used to be, and the input current usually has a lot of noise. Also, there is a lot of voltage stress on their output diodes, so they need diodes with a high breakdown voltage rating [26, 27]. Depending on the application, resonant dc-dc converters have advantages and disadvantages in terms of expense, complication, compactness, dependability, and efficiency. Better transformer utilization and strong dc voltage gains are provided by the current-fed resonant converter in [28]. Besides, the transformer’s leakage inductance is integrated into the converter’s basic workings as a resonant network, aiding in zero-current switching (ZCS) for the frond-side inverter switches. With its less component use, this converter is appropriate for low-power systems. In [29], a flyback topology for an RF, ZVS resonant PP converter is presented. It exhibits a high power density despite the high component count. More costs are required to reach a very high power density. This converter offers the same dc voltage gain ratio as the RF ZVS PP quasi-resonant converter in [30]. However, both converters’ dependability declines and complexity rises as a result of their three winding transformers and numerous switches [29, 30]. Many investigations have been conducted to get high gain by the application of the principles of diode-capacitor or diode-inductor cells [31–34]. Their sturdy and straightforward structures make it easy to use simpler control strategies. However, when voltage-cascaded stages increase, the majority of these converters experience increased voltage stress. For instance, the converter in [31], uses a voltage multiplier network based on FB cascaded diode capacitors to achieve a high voltage step-up ratio without the need for high-duty cycle operation. Furthermore, the voltage stress is comparatively smaller and is independent of the change in cascaded stages for capacitors, diodes, and switching devices. Nevertheless, this topology is not widely used because of the hard switching, low efficiency, and large boost inductance. A modified version of the converter [31], is suggested in [35], with an additional small inductance added between the FB legs. It provides cascaded stage independence, lower voltage stress, and a high conversion ratio. Additionally, by using a smaller cascaded capacitance and lower boost inductance, it achieves a slightly greater efficiency than the converter in [31]. However, soft switching operation was not achieved by this architecture. The literature review indicates a clear and ongoing need for resonant soft-switching high conversion ratio dc-dc converters that can provide substantial voltage gain at lower voltage stress with low ripples, specifically for low-voltage output energy sectors. This article proposes a full-bridge resonant cascaded (FBRC) dc-dc converter that offers minor ripples in output voltage and input current, compactness, improved efficiency, and less voltage stress on the FB switches. Moreover, it provides zero switching losses through the ZVS of the FB switches. Therefore, for low-voltage output sources like fuel cells, PV panels, and other renewable energy systems, this high-voltage step-up ratio converter can be a suitable component. The subsequent sections of this article are structured as follows: Section 2 elucidates the principles governing converter operation. In Section 3, a comparative analysis of performance is provided, coupled with discussions on the design considerations and parameter selection. Section 4 offers a concise depiction of the control mechanism employed in the proposed converter. Section 5 delineates the experimental results and their interpretation. The concluding remarks of the article are presented in Section 6. 2. Converter operation The full-bridge cascaded (FBC) converter reported in [35] has been improved by adding a resonant auxiliary circuit in place of the parallel inductor to achieve higher efficiency and ZVS operation. This section describes how this converter operates based on its different operating modes showing the current flow routes and optimal waveforms for each mode. The following presumptions are taken into account to streamline the analysis and operation smoothly: The converter operates in steady-state mode with n-stage of cascaded multiplier and continuous conduction mode (CCM). No losses and ripple are taken into account; all the passive and active devices are ideal. Because every capacitor utilized in this architecture is sufficiently large, every capacitor’s voltage is the same, except the first capacitor’s (C1) value, which is half that of the other capacitors. Fig 1 shows the developed high step-up FBRC converter. Low-voltage DC sources such as PV modules, FCs, batteries, DC power supplies, etc., can be used as the converter’s input. The converter in Fig 1 is built using an n-stage cascaded voltage multiplier, a resonant branch, and an FB cell comprising four switches designated SU1, SU2, SL1, and SL2, along with a boost input inductor (Ls). The resonant inductor (Lr1) is connected in series with the parallel capacitor (Cr)-inductor (Lr2) branch placed between the ac terminals (A and B) of the FB module. A single pair of diodes and a couple of capacitors make up a cascaded stage, whereas an n-stage contains 2n = N diodes and a comparable number of capacitors. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 1. Proposed Full-bridge resonant cascaded (FBRC) step-up dc-dc converter. https://doi.org/10.1371/journal.pone.0306906.g001 The resonant converter’s switching frequency is maintained close to its resonant frequency for optimal performance. Two distinct, independent frequencies are used to turn on and off the FB switches. Two distinct frequencies, designated as fSU and fSL, respectively, are used to operate the two upper switches (SU1 and SU2) and the two bottom switches (SL1 and SL2). A higher current can be supplied by the resonant branch to charge the FB switches’ bypass capacitors, achieving ZVS for both the upper and lower switches. To get the desired performance, the fSU is kept substantially lower than the fSL in this study, while the fSL is chosen as close to the resonant frequency as feasible. While fSU is maintained at a fixed value to achieve the necessary output voltage ripple, the duty cycle of fSL is adjusted within the resonance region to control the output voltage, Vo. Fig 2 illustrates the main wave shapes of the proposed converter for two cascaded stages and one switching period. It shows the FB MOSFET switching signals, the voltage across the FB terminal (vb), current ib, the resonance current ir, and the cascaded multiplier diode current ID1-ID4. Due to the alternating behaviour of ib, the suggested topology’s CCM working approaches can be split into two parts: one for the +ve interval and another for the -ve interval, with corresponding time lengths [To, TSU/2] and [TSU/2, TSU]. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 2. Key waveforms of the developed FBRC converter. https://doi.org/10.1371/journal.pone.0306906.g002 Only one diode conducts at order D4 followed by D2 in the positive half-cycle, and only one diode comes in conduction at order D3 followed by D1 in the other half-cycle. Furthermore, two operational modes, which are designated as Mode I and Mode II as displayed in Fig 3(A)–3(C) throughout this first half-cycle. Four distinct sections make up Mode II: Mode II-a, Mode II-b, Mode II-c and Mode II-d. As seen in Fig 4(A)–4(C), there are two working modes in the opposite interval of Mode III and Mode IV. Mode IV is further divided into four sub-modes, which are designated as Mode IV-a, Mode IV-b, Mode IV-c, and Mode IV-d. the n-stage diode-capacitor cascaded multipliers for which the proposed converter has undergone mathematical analysis have improved the converter’s applicability. Below is a detailed explanation of the circuit operation principles based on these operating modes. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 3. Current flow routes of the developed FBRC converter. (a) Operating Mode I. (b) Mode II-a. (c) Mode II-b. https://doi.org/10.1371/journal.pone.0306906.g003 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 4. Current flow routes of the developed FBRC converter. (a)Mode III. (b)Mode IV-a. (c) Mode IV-b. https://doi.org/10.1371/journal.pone.0306906.g004 Mode I (Fig 3(A)): In this stage, the high frequency switches SU1 is ON and SU2 is OFF, and all of the diodes of the voltage multiplier network are also switched OFF. At to, the high-frequency gating signals are applied to SL1 and SL2, and SL1 is turned ON when ZVS conditions are met. Through conducting switches SU1 and SL1, as well as the bypass diode of SL2, the boost inductor, resonant inductor, and capacitor are charged by the dc voltage source Vi. while C3 and C1 stay floating, the capacitors C4 and C2 provide current to the output. As seen in Fig 2, in this mode, the voltage across the FB terminal drops to zero, vb = 0 throughout the interval to < t < t1. As a result, the resonant current is fixed as: (1) where ir current passes through the resonant branch. On the other hand, the input boost inductor current can be found as follows: (2) where iSL1 is the current passes through the switch, SL1, and the resonant branch voltage is (3) Mode II: In Mode II, at t1, SL2 is turned ON under the ZVS condition while SU1 stays ON. Concurrently, at t1, the upper switch in the lagging leg SU2 remains OFF, and SL1 is turned OFF under ZVS condition. Energy for the cascaded network is provided by the boost inductor, resonant branch, and dc input voltage source through various even group diodes (D2 and D4). Since diodes D4 and D2 conduct in Mode II-a, as seen in Fig 3(B), the capacitors C2 and C4 are charged by the FB current ib; and this current also discharges the capacitors C1 and C3. As can be seen in in Fig 3(C), in the subsequent Mode II-b, diode D2 conducts, which causes ib to charge C2 and discharge C1; when C4 delivers to the load, C3 stays floating. The voltage across the FB terminal at this step, vb = Vo/2n occurs at the time interval t1 < t < t2. The expression for the input inductor current iLs is: (4) (5) (6) where Vi and vb stand for the voltages at the input dc source and FB output terminals A and B, respectively. The FB terminal voltage vb can be calculated as follows: (7) where vr1 and vCr are the voltages across the resonant circuit inductor and capacitor respectively. Therefore, the resonant voltage and current can be expressed as, (8) (9) ir is the resonant current, if the initial voltage , then Eq (8) becomes: (10) where the angular resonance frequency, and resonant impedance, . Therefore, the voltage across the resonant capacitor, vCr: (11) Combining Eqs (9) and (11), (12) From Eqs (5), (6) and (9), (13) As can be seen in Fig 2, there is an equal flow of current (ib) through diodes D2 and D4 throughout this time. Diode current may therefore be represented as follows using Eqs (5) and (13): (14) Mode II-c (t2 < t < t3): during this interval Mode I will recur, meaning that switches SU1 and SL1 are turned ON, and the other switches (SU2 and SL2) and all the multiplier diodes are switched OFF. As a result, each current expression will be the same as what is mentioned in Mode I. Mode II-d (t3 < t < t4): Mode II and Mode I will repeat one after the other during this period. Therefore, all of the current and voltage expressions should be the same as indicated above. Mode III (t4 < t < t5): During this phase, switch SU2 and SL2 are turned on, and the opposite switches (SU1 and SL1) and all cascaded circuit diodes are turned off. The high-frequency operating switches SL1 and SL2 also function under ZVS conditions. The input dc voltage charges the boost input inductance (Ls), the resonant inductor (Lr), and the capacitor via the switches SU2 and SL2, and the SL1 switch’s bypass diode, respectively. As revealed in Fig 4(A), the bottom capacitors (C4 and C2) transfer energy to the load similarly to Mode I, while C3 and C1 stay in the floating position. In this mode, the resonant branch current (ir) is fixed during the interval t4 < t < t5, and the voltage across the FB terminal drops to zero, i.e., vb = 0. Therefore, the boost inductor current can be calculated as: (15) where iSL1 is the current which flows through the switch, SL2. Mode IV: SU2 and SL1 are switched ON, and SU1 and SL2 are turned off. The inductances and input dc source transfer energy to the diode-capacitor voltage multiplier circuit through the conducting of diodes C3 and C1. In Mode IV-a, as seen in Fig 4(B), the diodes D3 and D1 conduct, as a result, the FB current discharges C2 and charges C3 and C1; and load is driven by the current of C4. In the subsequent Mode IV-b, diode D1 is in conduction, which causes, C1 to be charged by ib, the load current is provided by C4 and C2, and when C3 stays in a floating state as shown in Fig 4(C). During the interval t5 < t < t6, voltage across the FB terminal is vb = Vo/n, and the current ib can be expressed as follows: (16) (17) (18) The FB terminal voltage, vb can be determined as: (19) (20) (21) ir is the resonant current, then Eq (20) becomes: (22) As a result, voltage across the resonant capacitor vCr: (23) From Eqs (17), (18) and (21), (24) According to Fig 4(B), ib, current flows through both diodes (D1 and D3) equally at this time. Therefore, from Eqs (17) and (24), diode current can be expressed as: (25) Mode IV-c (t6 < t < t7): Mode III will recur in this interval, with switch SU2 and SL2 turned ON; and the other switches (SU1 and SL1) as well as all of the voltage multiplier network diodes are switched OFF. Hence, every current expression will be the same as what Mode III states. For t7 < t < t8, Mode IV-d: Modes IV and III will repeat in turn during this period. Therefore, every statement for current and voltage expression will ideally resemble those operating modes. The cycle will then begin once more after this. 3. Parameter design and selection The full-bridge resonant cascaded (FBRC) converter’s dc voltage gain is contingent on the duty cycle, resonant frequency, and high-frequency switches switching frequency. The link between these variables is explained in this section, along with how different components are designed taking into account their stress and permitted input current and output voltage ripples. Furthermore, the range of ZVS operation of the FB switches has been explained along with the resonance circuit across the FB terminal that supplies the resonance current needed to accomplish ZVS has also been described. The resonance current required for the FB switches to achieve ZVS is provided by the resonant circuit in series with an inductor (Lr) and a capacitor (Cr) across the FB terminal. Furthermore, the converter can operate under ZVS state from full load to 25% load to this design. 3.1 DC voltage conversion ratio and duty cycle The time durations (to-t1) and (t1-t2) are precisely equivalent to the time spans dTSL and (1-d) TSL, as seen in Fig 2, where d denotes duty ratio, and TSL (1/fSL) is the switching signal period of switches SL1 and SL2. To express the dc voltage conversion ratio of this converter, one can substitute dTSL and (1-d)TSL for the time in Eqs (2) and (6), and then use the volt-second balance strategy upon the boost inductor (Ls): (26) where kr = fSL/fr is the resonant constant, and fr is the resonant frequency. In a resonant converter, the switching frequency should ideally match the resonance frequency or kr = 1. In contrast, the switching frequency, fSL is controlled to maintain regulated output voltage. Therefore, the resonant constant value is kept as kr = 0.7~1.1 for ±10% variation of fSL. The voltage step-up gain of the suggested FBRC converter is compared with a few other converters described in the literature. It can be observed from Fig 5 that the voltage gain of this converter is higher than the other converters concerning the duty cycle. Also, although the component counts of this converter are slightly higher, the voltage step-up gain is higher compared to other converters except the converter described in [35], as shown in Fig 6. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 5. Voltage gain and duty cycle comparison. https://doi.org/10.1371/journal.pone.0306906.g005 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 6. Comparison of voltage gain and number of major components. https://doi.org/10.1371/journal.pone.0306906.g006 3.2 Inductor selection One important component of the suggested converter’s design that affects how much the input current ripples is the boost inductor. A fairly common nonlinear phenomenon is the PV array’s output changing the environmental conditions change. The suggested converter is made in a way that makes it ideal for a similar PV array. Nevertheless, ripple current has a massive impact on the PV array and significantly reduces its efficiency. The duty cycle must be raised as the Ls grows to control the output voltage and its ripple. Thus, the lowest possible input current ripple is taken into account together with the inductor’s size and cost. Boost input inductance (Ls) can be determined as follows: (27) where the input current ripple percentage and the maximum input current are designated by ΔiLs.pk and ILs.pk, respectively. From Eq (27) it is realized that this ripple relies on the boost input inductance and the operating frequency (fSL) of SL1 and SL2 for a given voltage gain (Mv) and duty cycle (d). The correlation between these factors is presented in Fig 7, where the solid line displays the boost input inductance versus input current’s ripple at the operating frequency, fSL is 80 kHz, and the input ripple vs this frequency is revealed by the triangle marked (dashed) line at inductance of Ls = 500 μH. In all scenarios, the current ripples are the same and amount to 5%. Hence, the boost inductor for this converter is assumed to be 500 μH for fSL and ΔiLs.pk are 80 kHz and 5%, respectively. The boost input inductance’s (Ls) maximum stored energy can be computed as follows: (28) The value can be computed as follows in the case of parallel inductance: (29) where ILp.pk and ΔiLp.pk indicate as the parallel inductance’s peak current and its percentage of ripple. The parallel inductance’s (Lp) maximum stored energy can also be computed as follows: (30) Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 7. Input current ripple versus input inductance. https://doi.org/10.1371/journal.pone.0306906.g007 3.3 Capacitor selection and voltage stress Except for the first capacitor, which has a voltage that is half of the others, all of the cascaded capacitors used in this design are suitably large and uniform in size, as was mentioned in the section above. Based on these presumptions, each capacitor’s voltage is as follows: (31) where the voltage of each capacitor, except the first (C1), is vc, and vcj represents the jth capacitor. From Fig 1, it is clear that voltage at the output terminal (Vo) is equal to the voltage total of all bottom capacitors (C2, C4, …,) and can be determined as: (32) Combining Eqs (31) and (32) the voltage of each capacitor of the voltage multiplier circuit for the n-stage can be stated as follows: (33) Therefore, according to Eq (33), the voltage multiplier capacitor’s maximum voltage stress is Vo.pk/2n, and for the first capacitor, it is Vo.pk/n, in which Vo.pk represents the output voltage’s peak value. The fifth row of Table 1 lists the voltage stresses for a single capacitor of this and alternative converter topologies. The value of the duty cycle and input dc voltage, as indicated in Table 1, are the only factors that affect the capacitor voltage stress for the recommended converter and the converter described in [31]. In contrast, the number of cascaded stages (n) of the other converters greatly influences the capacitor voltage stress. Download: PPT PowerPoint slide PNG larger image TIFF original image Table 1. Comparison among conventional high voltage step-up ratio converters with the suggested converter. https://doi.org/10.1371/journal.pone.0306906.t001 Fig 8 illustrates voltage strains on the capacitor for this converter and a few others at a constant duty ratio, d = 0.5 and a constant output voltage, Vo = 380 V. Therefore, it can be seen from the voltage step-up gain equation of these architectures listed in Table 1 that the number of stages increases, the required input voltage declines. For instance, if there are two stages, (n = 2), and constant d = 0.5 and constant Vo = 380 V, the proposed converter input voltage is 31.67 V, whereas the converter reported in [34] requires a higher voltage, which is 76 V. As a result, the suggested topology has a lower capacitor voltage stress than the later one and also lower compared to the other converters up to the number of voltage multiplier stages, n = 2 as displayed in Fig 8. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 8. Comparison of the voltage stresses on the capacitor of the proposed and other converters. https://doi.org/10.1371/journal.pone.0306906.g008 The voltage across the capacitors about duty ratio can be stated as follows from Eqs (33) and (26) by considering the ideal value of kr = 1: (34) As can be observed from Eq (34), unlike the other converter topologies described in the literature, the individual capacitor voltage of this converter fluctuates with variations in the Vi and d rather than the number of voltage multiplier stages. Although all capacitor voltages are equal in theory, it is impossible to ignore the voltage drops and ripples that occur when a capacitor is loaded. The ripple voltage of each specific capacitor is as follows, according to the current-fed investigation [36], which is not as much of intricate as the corresponding voltage-fed study [37, 38]: (35) where TSU and Io.av stand for the time duration of the alternating frequency and the average output current, respectively. The ripple of the output voltage for a given current output and the number of voltage multiplier stages can be observed from Eq (35) depending on the gate signal frequency (fSU) of the upper two switches (SU1 and SU2) as well as the foot side capacitance. Fig 9 represents the correlations between these factors. The solid line in Fig 9 indicates the capacitance versus ripple voltage at a given operating frequency, fSU is 9 kHz. Additionally, the operating frequency, fSU versus ripple is displayed by the triangle marked dashed line at the given capacitance value, C = 50 μF. The ripple of the output voltage should be the same 0.76% in both scenarios. Therefore, for switching frequency, fSU, is 9 kHz and ΔvC, is 0.76%, the capacitance is chosen as 50 μF for this suggested converter. There is a little bit of voltage unbalance in the multiplier capacitor as revealed in Fig 10. At capacitance 50 μF, voltage imbalance is found as 0.2%. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 9. Capacitor voltage and output voltage ripple. https://doi.org/10.1371/journal.pone.0306906.g009 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 10. Voltage unbalanced ripple on the capacitor. https://doi.org/10.1371/journal.pone.0306906.g010 The stored energy in capacitance can be given by: (36) By submitting Eqs (34) and (35) into Eq (36), (37) 3.4 Switch’s voltage and current stresses The highest voltage stress of the diode is twice that of the gate switches which is Vo.pk/2n, and the extreme stress of current is Ib.pk/n, where Ib.pk is the peak current input of the voltage multiplier circuit. Two diodes are on at once. The switch’s voltage stress is represented in Fig 11. It is lower for this suggested converter than others except the converter reported in [39]. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 11. Voltage stress on switch of the proposed FBRC converter. https://doi.org/10.1371/journal.pone.0306906.g011 Table 2 represents the performance such as the output power, efficiency, voltage ripple, current ripple, voltage gain, and duty ratio of some boost-type dc-dc converters suitable for renewable energy (e.g., PV, FC, etc.) applications compared with the suggested converter. The voltage gain is higher for the converter in [40] than the others, whereas the ON time of the switch(s) is kept lower for the proposed converter. In addition, the measured efficiency is higher than all other converters. Furthermore, the converter in [41], offers the least output voltage ripple; however, it suffers from poor efficiency at the rated power. The output voltage and input current ripples are much higher in the converter [18] than that of the developed converter. Moreover, the proposed converter’s output power, voltage gain, efficiency, and ripples are better than the converter described in [35]. Download: PPT PowerPoint slide PNG larger image TIFF original image Table 2. Comparison among the output power, duty cycle, voltage gain, voltage and current ripples, and efficiency of different dc-dc converters. https://doi.org/10.1371/journal.pone.0306906.t002 3.5 Condition and range for ZVS of the switches As seen in Fig 3, the ZVS current of switch SL2 is the difference between the bridge current (ib) and the auxiliary resonant branch current (ir) at t2. On the other hand, as Fig 3(E) illustrates, the ZVS current of switch SL1 is the result of a combination of the bridge current (ib) and the auxiliary resonant branch current (ir) at t6. Given that the operating frequencies of these two switches are the same (t1 = t2 = t6). As a result, these two currents have the same RMS value. Therefore, (38) The following requirements must be met for SL1 and SL2’s ZVS to switch on and off: (39) It is clear from Fig 3 that the RMS current (ISU.ZVS) flowing through the upper two switches (SU1 and SU2) has the same magnitude as ISL.ZVS. However, current flow through these switches for a longer period than t1 is approximately 8.89 times longer (8.89 is the frequency ratio of fSL and fSU for this study). Consequently, the lower frequency switches (SU1 and SU2) likewise operate securely under ZVS conditions across the whole operational range. 3.1 DC voltage conversion ratio and duty cycle The time durations (to-t1) and (t1-t2) are precisely equivalent to the time spans dTSL and (1-d) TSL, as seen in Fig 2, where d denotes duty ratio, and TSL (1/fSL) is the switching signal period of switches SL1 and SL2. To express the dc voltage conversion ratio of this converter, one can substitute dTSL and (1-d)TSL for the time in Eqs (2) and (6), and then use the volt-second balance strategy upon the boost inductor (Ls): (26) where kr = fSL/fr is the resonant constant, and fr is the resonant frequency. In a resonant converter, the switching frequency should ideally match the resonance frequency or kr = 1. In contrast, the switching frequency, fSL is controlled to maintain regulated output voltage. Therefore, the resonant constant value is kept as kr = 0.7~1.1 for ±10% variation of fSL. The voltage step-up gain of the suggested FBRC converter is compared with a few other converters described in the literature. It can be observed from Fig 5 that the voltage gain of this converter is higher than the other converters concerning the duty cycle. Also, although the component counts of this converter are slightly higher, the voltage step-up gain is higher compared to other converters except the converter described in [35], as shown in Fig 6. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 5. Voltage gain and duty cycle comparison. https://doi.org/10.1371/journal.pone.0306906.g005 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 6. Comparison of voltage gain and number of major components. https://doi.org/10.1371/journal.pone.0306906.g006 3.2 Inductor selection One important component of the suggested converter’s design that affects how much the input current ripples is the boost inductor. A fairly common nonlinear phenomenon is the PV array’s output changing the environmental conditions change. The suggested converter is made in a way that makes it ideal for a similar PV array. Nevertheless, ripple current has a massive impact on the PV array and significantly reduces its efficiency. The duty cycle must be raised as the Ls grows to control the output voltage and its ripple. Thus, the lowest possible input current ripple is taken into account together with the inductor’s size and cost. Boost input inductance (Ls) can be determined as follows: (27) where the input current ripple percentage and the maximum input current are designated by ΔiLs.pk and ILs.pk, respectively. From Eq (27) it is realized that this ripple relies on the boost input inductance and the operating frequency (fSL) of SL1 and SL2 for a given voltage gain (Mv) and duty cycle (d). The correlation between these factors is presented in Fig 7, where the solid line displays the boost input inductance versus input current’s ripple at the operating frequency, fSL is 80 kHz, and the input ripple vs this frequency is revealed by the triangle marked (dashed) line at inductance of Ls = 500 μH. In all scenarios, the current ripples are the same and amount to 5%. Hence, the boost inductor for this converter is assumed to be 500 μH for fSL and ΔiLs.pk are 80 kHz and 5%, respectively. The boost input inductance’s (Ls) maximum stored energy can be computed as follows: (28) The value can be computed as follows in the case of parallel inductance: (29) where ILp.pk and ΔiLp.pk indicate as the parallel inductance’s peak current and its percentage of ripple. The parallel inductance’s (Lp) maximum stored energy can also be computed as follows: (30) Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 7. Input current ripple versus input inductance. https://doi.org/10.1371/journal.pone.0306906.g007 3.3 Capacitor selection and voltage stress Except for the first capacitor, which has a voltage that is half of the others, all of the cascaded capacitors used in this design are suitably large and uniform in size, as was mentioned in the section above. Based on these presumptions, each capacitor’s voltage is as follows: (31) where the voltage of each capacitor, except the first (C1), is vc, and vcj represents the jth capacitor. From Fig 1, it is clear that voltage at the output terminal (Vo) is equal to the voltage total of all bottom capacitors (C2, C4, …,) and can be determined as: (32) Combining Eqs (31) and (32) the voltage of each capacitor of the voltage multiplier circuit for the n-stage can be stated as follows: (33) Therefore, according to Eq (33), the voltage multiplier capacitor’s maximum voltage stress is Vo.pk/2n, and for the first capacitor, it is Vo.pk/n, in which Vo.pk represents the output voltage’s peak value. The fifth row of Table 1 lists the voltage stresses for a single capacitor of this and alternative converter topologies. The value of the duty cycle and input dc voltage, as indicated in Table 1, are the only factors that affect the capacitor voltage stress for the recommended converter and the converter described in [31]. In contrast, the number of cascaded stages (n) of the other converters greatly influences the capacitor voltage stress. Download: PPT PowerPoint slide PNG larger image TIFF original image Table 1. Comparison among conventional high voltage step-up ratio converters with the suggested converter. https://doi.org/10.1371/journal.pone.0306906.t001 Fig 8 illustrates voltage strains on the capacitor for this converter and a few others at a constant duty ratio, d = 0.5 and a constant output voltage, Vo = 380 V. Therefore, it can be seen from the voltage step-up gain equation of these architectures listed in Table 1 that the number of stages increases, the required input voltage declines. For instance, if there are two stages, (n = 2), and constant d = 0.5 and constant Vo = 380 V, the proposed converter input voltage is 31.67 V, whereas the converter reported in [34] requires a higher voltage, which is 76 V. As a result, the suggested topology has a lower capacitor voltage stress than the later one and also lower compared to the other converters up to the number of voltage multiplier stages, n = 2 as displayed in Fig 8. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 8. Comparison of the voltage stresses on the capacitor of the proposed and other converters. https://doi.org/10.1371/journal.pone.0306906.g008 The voltage across the capacitors about duty ratio can be stated as follows from Eqs (33) and (26) by considering the ideal value of kr = 1: (34) As can be observed from Eq (34), unlike the other converter topologies described in the literature, the individual capacitor voltage of this converter fluctuates with variations in the Vi and d rather than the number of voltage multiplier stages. Although all capacitor voltages are equal in theory, it is impossible to ignore the voltage drops and ripples that occur when a capacitor is loaded. The ripple voltage of each specific capacitor is as follows, according to the current-fed investigation [36], which is not as much of intricate as the corresponding voltage-fed study [37, 38]: (35) where TSU and Io.av stand for the time duration of the alternating frequency and the average output current, respectively. The ripple of the output voltage for a given current output and the number of voltage multiplier stages can be observed from Eq (35) depending on the gate signal frequency (fSU) of the upper two switches (SU1 and SU2) as well as the foot side capacitance. Fig 9 represents the correlations between these factors. The solid line in Fig 9 indicates the capacitance versus ripple voltage at a given operating frequency, fSU is 9 kHz. Additionally, the operating frequency, fSU versus ripple is displayed by the triangle marked dashed line at the given capacitance value, C = 50 μF. The ripple of the output voltage should be the same 0.76% in both scenarios. Therefore, for switching frequency, fSU, is 9 kHz and ΔvC, is 0.76%, the capacitance is chosen as 50 μF for this suggested converter. There is a little bit of voltage unbalance in the multiplier capacitor as revealed in Fig 10. At capacitance 50 μF, voltage imbalance is found as 0.2%. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 9. Capacitor voltage and output voltage ripple. https://doi.org/10.1371/journal.pone.0306906.g009 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 10. Voltage unbalanced ripple on the capacitor. https://doi.org/10.1371/journal.pone.0306906.g010 The stored energy in capacitance can be given by: (36) By submitting Eqs (34) and (35) into Eq (36), (37) 3.4 Switch’s voltage and current stresses The highest voltage stress of the diode is twice that of the gate switches which is Vo.pk/2n, and the extreme stress of current is Ib.pk/n, where Ib.pk is the peak current input of the voltage multiplier circuit. Two diodes are on at once. The switch’s voltage stress is represented in Fig 11. It is lower for this suggested converter than others except the converter reported in [39]. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 11. Voltage stress on switch of the proposed FBRC converter. https://doi.org/10.1371/journal.pone.0306906.g011 Table 2 represents the performance such as the output power, efficiency, voltage ripple, current ripple, voltage gain, and duty ratio of some boost-type dc-dc converters suitable for renewable energy (e.g., PV, FC, etc.) applications compared with the suggested converter. The voltage gain is higher for the converter in [40] than the others, whereas the ON time of the switch(s) is kept lower for the proposed converter. In addition, the measured efficiency is higher than all other converters. Furthermore, the converter in [41], offers the least output voltage ripple; however, it suffers from poor efficiency at the rated power. The output voltage and input current ripples are much higher in the converter [18] than that of the developed converter. Moreover, the proposed converter’s output power, voltage gain, efficiency, and ripples are better than the converter described in [35]. Download: PPT PowerPoint slide PNG larger image TIFF original image Table 2. Comparison among the output power, duty cycle, voltage gain, voltage and current ripples, and efficiency of different dc-dc converters. https://doi.org/10.1371/journal.pone.0306906.t002 3.5 Condition and range for ZVS of the switches As seen in Fig 3, the ZVS current of switch SL2 is the difference between the bridge current (ib) and the auxiliary resonant branch current (ir) at t2. On the other hand, as Fig 3(E) illustrates, the ZVS current of switch SL1 is the result of a combination of the bridge current (ib) and the auxiliary resonant branch current (ir) at t6. Given that the operating frequencies of these two switches are the same (t1 = t2 = t6). As a result, these two currents have the same RMS value. Therefore, (38) The following requirements must be met for SL1 and SL2’s ZVS to switch on and off: (39) It is clear from Fig 3 that the RMS current (ISU.ZVS) flowing through the upper two switches (SU1 and SU2) has the same magnitude as ISL.ZVS. However, current flow through these switches for a longer period than t1 is approximately 8.89 times longer (8.89 is the frequency ratio of fSL and fSU for this study). Consequently, the lower frequency switches (SU1 and SU2) likewise operate securely under ZVS conditions across the whole operational range. 4. Control technique This section describes the control technique of the proposed converter in brief. The proposed converter operates similarly to the classic boost converter, except for the alternating voltage (vb) and current (ib) generated across the full-bridge terminal. Due to the cost-effectiveness, fast processing speed, and user-friendly application, the DSP chip has generated control signals for the designed converter. The suggested converters utilize a two-independent-frequency variable-duty cycle PWM modulation technique to generate the gate signals. The FB module has four switches, SU1, SU2, SL1, and SL2, as depicted in Fig 12(A). SU1 (SL1) and SU2 (SL2) work in a complementary manner, with SU1’s switching frequency denoted as fSU and SL1’s switching frequency marked as fSL, as shown in Fig 12(B). fSU and fSL are designated as the alternating frequency and modulating frequency, respectively, for the sake of ease. Ideally, choosing these two frequencies as high as possible is necessary to minimize the usage of lower values of passive components (capacitor and inductor) in the circuit. This study achieves the desired output by maintaining a significantly lower frequency for fSU compared to fSL. The output voltage Vo is controlled by adjusting the duty ratio of fSL, while fSU determines the ripple of Vo. Furthermore, the fSL to fSU ratio must be an odd number (an integer or a fraction). Specifically, if the ratio (fSL/fSU) is not an even integer F, the voltage across the FB (vb) will be unidirectional instead of alternating. This is because two switches of the same FB lag, SU1 and SL1 or SU2 and SL2, will turn on simultaneously at the transition of fSU. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 12. (a) Full-bridge module. (b) Control gate signals of the full-bridge module of the proposed converter. https://doi.org/10.1371/journal.pone.0306906.g012 4.1 PID controller design The state-space averaging methodology is commonly employed to design linear controllers for dc-dc converters due to its ability to integrate the advantages of both state-space and averaging methods. It uses the inductor current and capacitor voltage as separate variables. This converter’s continuous time-domain transfer function can be expressed using the state-space averaging technique as follows: (40) where Vo, Ro and Co represent the output voltage, load resistance, and output filter capacitance, respectively. The duty cycle, represented by d, measures the ratio of the on-time to the total time of a periodic signal. RC and LC represent the equivalent series resistance (ESR) and equivalent series inductance (ESL) of Co and C components, respectively. Here, C equals C1 and C3, while Co equals the parallel combination of C2 and C4. To simplify the analysis, the equivalent series inductance (ESL) of the capacitor and the equivalent series resistance (ESR) of the inductor are ignored. and represent the minor fluctuations in the output voltage and duty cycle, respectively, and Le = LC/(1−d)2. The parameters’ values can be found in Tables 3 and 4, as well as in their respective data sheets. Upon submitting these values, the control to output transfer function at the nominal operating point is determined as: (41) Download: PPT PowerPoint slide PNG larger image TIFF original image Table 3. The proposed converter prototype’s specifications. https://doi.org/10.1371/journal.pone.0306906.t003 Download: PPT PowerPoint slide PNG larger image TIFF original image Table 4. Description of suggested converter prototype’s components. https://doi.org/10.1371/journal.pone.0306906.t004 The PID controller, a lead-lag compensator, is extensively employed in feedback control systems. Thus, the PID controller is selected to regulate the proposed converters. The PID controller can be defined as: (42) where e(t) and m(t) represent the input and output of the compensator, respectively. The Laplace transform of the transfer function described in Eq (42) can be expressed as: (43) This continuous time domain transfer function is converted to a discrete-time domain to implement in the DSP controller. Therefore, the digital transfer function of the PID controller can be derived as follows: (44) The z-domain transfer function of the PID controller in Eq (44) needs to be transformed into a difference equation to generate a new duty cycle for the digital PID controller using DSP. The difference equation can be expressed as: (45) where u[k] and e[k] represent the controller output and output error, respectively, for the kth sample. The various parameter values are located in the experiment and data sheets. Fig 13 displays the block diagram of the control technique used in this converter. The voltage sensor measures the output voltage and transmits it to the DSP module. The digital signal processor (DSP) produces switching gate signals for the FB MOSFET by comparing the output voltage (Vo) with the reference voltage (Vref), using the PID controller technique. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 13. Block diagram of the control technique of the proposed converter. https://doi.org/10.1371/journal.pone.0306906.g013 4.1 PID controller design The state-space averaging methodology is commonly employed to design linear controllers for dc-dc converters due to its ability to integrate the advantages of both state-space and averaging methods. It uses the inductor current and capacitor voltage as separate variables. This converter’s continuous time-domain transfer function can be expressed using the state-space averaging technique as follows: (40) where Vo, Ro and Co represent the output voltage, load resistance, and output filter capacitance, respectively. The duty cycle, represented by d, measures the ratio of the on-time to the total time of a periodic signal. RC and LC represent the equivalent series resistance (ESR) and equivalent series inductance (ESL) of Co and C components, respectively. Here, C equals C1 and C3, while Co equals the parallel combination of C2 and C4. To simplify the analysis, the equivalent series inductance (ESL) of the capacitor and the equivalent series resistance (ESR) of the inductor are ignored. and represent the minor fluctuations in the output voltage and duty cycle, respectively, and Le = LC/(1−d)2. The parameters’ values can be found in Tables 3 and 4, as well as in their respective data sheets. Upon submitting these values, the control to output transfer function at the nominal operating point is determined as: (41) Download: PPT PowerPoint slide PNG larger image TIFF original image Table 3. The proposed converter prototype’s specifications. https://doi.org/10.1371/journal.pone.0306906.t003 Download: PPT PowerPoint slide PNG larger image TIFF original image Table 4. Description of suggested converter prototype’s components. https://doi.org/10.1371/journal.pone.0306906.t004 The PID controller, a lead-lag compensator, is extensively employed in feedback control systems. Thus, the PID controller is selected to regulate the proposed converters. The PID controller can be defined as: (42) where e(t) and m(t) represent the input and output of the compensator, respectively. The Laplace transform of the transfer function described in Eq (42) can be expressed as: (43) This continuous time domain transfer function is converted to a discrete-time domain to implement in the DSP controller. Therefore, the digital transfer function of the PID controller can be derived as follows: (44) The z-domain transfer function of the PID controller in Eq (44) needs to be transformed into a difference equation to generate a new duty cycle for the digital PID controller using DSP. The difference equation can be expressed as: (45) where u[k] and e[k] represent the controller output and output error, respectively, for the kth sample. The various parameter values are located in the experiment and data sheets. Fig 13 displays the block diagram of the control technique used in this converter. The voltage sensor measures the output voltage and transmits it to the DSP module. The digital signal processor (DSP) produces switching gate signals for the FB MOSFET by comparing the output voltage (Vo) with the reference voltage (Vref), using the PID controller technique. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 13. Block diagram of the control technique of the proposed converter. https://doi.org/10.1371/journal.pone.0306906.g013 5. Experimental outcomes To validate the theoretical analysis for the developed FB resonant cascaded (FBRC) dc-dc converter, a 500 W laboratory prototype of two cascaded stages is implemented. The figure of the experimental setup indicating all apparatus is displayed in Fig 14. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 14. FBRC converter hardware implementation. https://doi.org/10.1371/journal.pone.0306906.g014 To get the intended output voltage, Vo = 400 V, a broad range of input voltages (40 ~ 80 V) is applied. The duty ratio of the gate switching frequency (fSL) is adjusted between 0.45 ~ 0.6. The Texas Instrument TMS320F28335 controller generates and controls the switching signals. Tables 3 and 4 list the component values following the design process and the various parameters employed in the developed converter. 5.1 Result analysis of FBRC converter The simulation results of the suggested Full-bridge resonant cascaded (FBRC) converter in the steady-state mode are illustrated in Fig 15. The gate signals of the FB switches SSU1, SSU2, SSL1, and SSL2, where the first two of these have an alternating frequency fSU (9 kHz), while the second two use a higher frequency fSL (80 kHz). Fig 15 also demonstrates the simulation outcomes of the FB circuit terminal voltage (vb), and resonant current (ir) along with the output voltage (Vo), output current (Io), and input current (iLS). Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 15. Simulation waves of Vb and ir, output voltage and current, Vo and Io, and input current iLs. https://doi.org/10.1371/journal.pone.0306906.g015 The experimental findings are displayed in Figs 16–28. Fig 16 represents the gate signals of the four FB MOSFET devices, while Fig 17 displays the vb and ir. The converter switch operates on ZVS even in the non-resonant condition (fSL ≠ fr, where fr is the resonance frequency), and a voltage spike forms across the switch, as illustrated in Fig 18, at this moment, the switching frequency (fSL) is slightly increased, from 80 kHz to 88 kHz. However, if the difference of these frequencies is much higher, for instance, fSL < fr/2 and fr/2< fSL < fr, all FB switches operate in a hard-switching state. As a result, lower voltage gain resulting reduced output voltage. In addition, voltage spikes appear at the turn-on and turn-off transitions, as presented in Figs 19 and 20. In Fig 21, the frequency ratio versus voltage gain behaviour is presented, where, voltage gain is 12, at the unity frequency ratio, and then it drops with the frequency ratio declines, and rises at a frequency ratio that is somewhat larger than unity, and subsequently falls again. On the other hand, converter switches operate complete ZVS at the resonant frequency. Figs 22 and 23 depict the ZVS operations of the high-frequency switch SL1, whereas Fig 22 illustrates the ZVS operation during turn-on and turn-off at a 25% load condition. On the other hand, Fig 23 presents the ZVS operation during turn-on and turn-off at 100% load. Similar to this, the other complementary switch, SL2, also operates in the same load range and under ZVS conditions without any incident. Furthermore, the ZVS operations of the low frequency switch SU1 at 25% and 100% load are exposed in Figs 24 and 25, respectively. Additionally, there isn’t any voltage spike in the transitions of the high and low-frequency switches as well. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 16. Experimental switching signals of the four FB MOSFET gates. https://doi.org/10.1371/journal.pone.0306906.g016 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 17. Experimental results of FB voltage (vb) and resonant current (ir). https://doi.org/10.1371/journal.pone.0306906.g017 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 18. ZVS turn-off and turn-on with voltage spike at fSL(88kHz) > fr(80kHz) of the switch SL1. https://doi.org/10.1371/journal.pone.0306906.g018 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 19. Turn-off and turn-on with hard switching at fSL(38 kHz) < fr/2 of the switch SL1. https://doi.org/10.1371/journal.pone.0306906.g019 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 20. Turn-off and turn-on with hard switching at fr/2 < fSL(50 kHz) < fr of the switch SL1. https://doi.org/10.1371/journal.pone.0306906.g020 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 21. Voltage gain versus frequency ratio. https://doi.org/10.1371/journal.pone.0306906.g021 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 22. ZVS turn-off and turn-on operation at 25% load of SL1. https://doi.org/10.1371/journal.pone.0306906.g022 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 23. ZVS turn-off and turn-on operation at 100% load of SL1. https://doi.org/10.1371/journal.pone.0306906.g023 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 24. ZVS turn-off and turn-on operation at 25% load of SU1. https://doi.org/10.1371/journal.pone.0306906.g024 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 25. ZVS turn-off and turn-on operation at 100% load of SU1. https://doi.org/10.1371/journal.pone.0306906.g025 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 26. Experimental dynamic response of the PID controller due to load changes. (a) Load increased from 50% to 100%. (b) Load decreased from 100% to 50%. https://doi.org/10.1371/journal.pone.0306906.g026 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 27. Experimental dynamic responses of the PID controller due to input voltage variations. (a) Input voltage increased from 60V to 70V. (b) Input voltage decreased from 60V to 50V. https://doi.org/10.1371/journal.pone.0306906.g027 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 28. Experimental output voltage, input boost inductor current, and output current. https://doi.org/10.1371/journal.pone.0306906.g028 The dynamic response of this converter for the PID controller to variation in load is represented in Fig 26. When the load is increased from 50% to 100%, the output voltage first slightly drops before increasing for a few milliseconds (ms) to stabilize at the ideal 400 V. It takes about 32 ms (approx.) for the disturbance to stabilize in total. Similar to this, when the load is reduced from 100% to 50%, the output voltage first increases somewhat before stabilizing. Fig 27 displays the PID controller’s dynamic behaviour in the variations of the input voltage. It shows that when the input voltage is slightly increased, the output voltage rises at first before falling back to its starting value and becoming steady. Furthermore, the experimental output voltage (Vo), current (Io), and input inductor current (iLs) are presented in Fig 28. There is good agreement between the experimental and the simulation outcomes. 5.2 Loss and efficiency analysis This subsection provides a concise, step-by-step description of the power loss calculation among the main components and a brief efficiency analysis of the suggested converter. Initially, the power loss of a MOSFET switching device can be written as follows (46) where Ps(mos) and Pcon(mos) are the MOSFET switching and conduction losses, respectively. Since each FB switch of this converter operates ZVS, the switching loss is optimally negligible. Therefore, we can consider only the conduction loss, and it can be stated as: (47) The variables and Rds(ON) represents the RMS current flowing through the MOSFET and the ON state resistance of the MOSFET, respectively. Hence, based on the experiential data and datasheet of the C3M0120090D MOSFET utilized in this study, the total power losses of four FB switches can be determined as follows: (48) The power dissipated by a diode can be calculated by multiplying its forward voltage drop, VF, by the average current, Id(avg), that flows through it during one switching cycle. Therefore, based on the datasheet of the IDH10S120 diode and the average current obtained from the experiment, the diode’s (four diodes) total losses may be determined. (49) The power dissipation of the B32776G4506K000 film capacitor utilized in this study can be computed using the following formula: (50) Hence, the total capacitor power loss will be the sum of four cascaded multiplier capacitors loss and one resonant branch capacitor loss: (51) The inductor loss is the sum of the core loss, PL(core), and the winding loss, PL(wind). The calculation of PL(core) involves multiplying the effective volume of the core, Ve, by the core loss per unit volume, P(c/v), according to the following formula: (52) Again, the inductor winding loss can be expressed as: (53) The variables IL(avg), IL(ac-rms), IL(pk-pk), and Rdc represent the average current, ac rms current, peak-peak ripple current magnitude, and winding dc resistance of the inductor, respectively. The VISHAY IHV15BZ500 and two BOURNS JW MILLER 1130-101K-RC devices are utilized in this study as the input boost inductor and resonant branch inductors, respectively. Therefore, based on the testing results and the inductor data sheet, the total inductor losses can be determined as follows: (54) Therefore, the total calculated power loss of the developed converter is (55) The experiment yielded a measured power loss of 16.80 W, which is marginally lower than the above-calculated power loss. The power loss for the diode and capacitor is determined based on a temperature of 25°C. Nevertheless, the temperature at the junction of these devices rises as power is dissipated, reducing the diode’s forward voltage drop and the capacitor’s equivalent series resistance (ESR). Consequently, there is a decrease in power loss. The loss distribution of the key apparatuses of the suggested converter is displayed in Fig 29. The switching loss is optimally negligible because every FB switch operates in a ZVS state. On the other hand, the switch conduction loss, which is 32%, is the highest contribution. The inductor and diode losses are close, 23% and 24%, respectively. The least contribution comes from the capacitor, which is 21%. Fig 30 demonstrates the efficiency of the FBRC converter, considering different load conditions and input voltages (40, 60, and 80 V). The input and output currents and voltages are measured using two oscilloscope current probes and multimeters to determine the converter’s efficiency. The system’s peak efficiency is 95.8% when a load of 400 W is connected, and an input voltage of 60 V is applied. This efficiency is achieved when the output voltage is set to 400 V. In addition, Fig 31 presents the effect of the duty ratio on the converter’s efficiency. The converter’s efficiency is also lower at a low duty ratio because the lower output voltage causes higher current resulting in more power loss. Again, at a higher duty ratio, converter efficiency is also lower. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 29. Estimated power losses of different main components used in this converter. https://doi.org/10.1371/journal.pone.0306906.g029 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 30. Converter measured efficiency at various loads. https://doi.org/10.1371/journal.pone.0306906.g030 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 31. Measured efficiency vs duty cycle. https://doi.org/10.1371/journal.pone.0306906.g031 5.1 Result analysis of FBRC converter The simulation results of the suggested Full-bridge resonant cascaded (FBRC) converter in the steady-state mode are illustrated in Fig 15. The gate signals of the FB switches SSU1, SSU2, SSL1, and SSL2, where the first two of these have an alternating frequency fSU (9 kHz), while the second two use a higher frequency fSL (80 kHz). Fig 15 also demonstrates the simulation outcomes of the FB circuit terminal voltage (vb), and resonant current (ir) along with the output voltage (Vo), output current (Io), and input current (iLS). Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 15. Simulation waves of Vb and ir, output voltage and current, Vo and Io, and input current iLs. https://doi.org/10.1371/journal.pone.0306906.g015 The experimental findings are displayed in Figs 16–28. Fig 16 represents the gate signals of the four FB MOSFET devices, while Fig 17 displays the vb and ir. The converter switch operates on ZVS even in the non-resonant condition (fSL ≠ fr, where fr is the resonance frequency), and a voltage spike forms across the switch, as illustrated in Fig 18, at this moment, the switching frequency (fSL) is slightly increased, from 80 kHz to 88 kHz. However, if the difference of these frequencies is much higher, for instance, fSL < fr/2 and fr/2< fSL < fr, all FB switches operate in a hard-switching state. As a result, lower voltage gain resulting reduced output voltage. In addition, voltage spikes appear at the turn-on and turn-off transitions, as presented in Figs 19 and 20. In Fig 21, the frequency ratio versus voltage gain behaviour is presented, where, voltage gain is 12, at the unity frequency ratio, and then it drops with the frequency ratio declines, and rises at a frequency ratio that is somewhat larger than unity, and subsequently falls again. On the other hand, converter switches operate complete ZVS at the resonant frequency. Figs 22 and 23 depict the ZVS operations of the high-frequency switch SL1, whereas Fig 22 illustrates the ZVS operation during turn-on and turn-off at a 25% load condition. On the other hand, Fig 23 presents the ZVS operation during turn-on and turn-off at 100% load. Similar to this, the other complementary switch, SL2, also operates in the same load range and under ZVS conditions without any incident. Furthermore, the ZVS operations of the low frequency switch SU1 at 25% and 100% load are exposed in Figs 24 and 25, respectively. Additionally, there isn’t any voltage spike in the transitions of the high and low-frequency switches as well. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 16. Experimental switching signals of the four FB MOSFET gates. https://doi.org/10.1371/journal.pone.0306906.g016 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 17. Experimental results of FB voltage (vb) and resonant current (ir). https://doi.org/10.1371/journal.pone.0306906.g017 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 18. ZVS turn-off and turn-on with voltage spike at fSL(88kHz) > fr(80kHz) of the switch SL1. https://doi.org/10.1371/journal.pone.0306906.g018 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 19. Turn-off and turn-on with hard switching at fSL(38 kHz) < fr/2 of the switch SL1. https://doi.org/10.1371/journal.pone.0306906.g019 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 20. Turn-off and turn-on with hard switching at fr/2 < fSL(50 kHz) < fr of the switch SL1. https://doi.org/10.1371/journal.pone.0306906.g020 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 21. Voltage gain versus frequency ratio. https://doi.org/10.1371/journal.pone.0306906.g021 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 22. ZVS turn-off and turn-on operation at 25% load of SL1. https://doi.org/10.1371/journal.pone.0306906.g022 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 23. ZVS turn-off and turn-on operation at 100% load of SL1. https://doi.org/10.1371/journal.pone.0306906.g023 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 24. ZVS turn-off and turn-on operation at 25% load of SU1. https://doi.org/10.1371/journal.pone.0306906.g024 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 25. ZVS turn-off and turn-on operation at 100% load of SU1. https://doi.org/10.1371/journal.pone.0306906.g025 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 26. Experimental dynamic response of the PID controller due to load changes. (a) Load increased from 50% to 100%. (b) Load decreased from 100% to 50%. https://doi.org/10.1371/journal.pone.0306906.g026 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 27. Experimental dynamic responses of the PID controller due to input voltage variations. (a) Input voltage increased from 60V to 70V. (b) Input voltage decreased from 60V to 50V. https://doi.org/10.1371/journal.pone.0306906.g027 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 28. Experimental output voltage, input boost inductor current, and output current. https://doi.org/10.1371/journal.pone.0306906.g028 The dynamic response of this converter for the PID controller to variation in load is represented in Fig 26. When the load is increased from 50% to 100%, the output voltage first slightly drops before increasing for a few milliseconds (ms) to stabilize at the ideal 400 V. It takes about 32 ms (approx.) for the disturbance to stabilize in total. Similar to this, when the load is reduced from 100% to 50%, the output voltage first increases somewhat before stabilizing. Fig 27 displays the PID controller’s dynamic behaviour in the variations of the input voltage. It shows that when the input voltage is slightly increased, the output voltage rises at first before falling back to its starting value and becoming steady. Furthermore, the experimental output voltage (Vo), current (Io), and input inductor current (iLs) are presented in Fig 28. There is good agreement between the experimental and the simulation outcomes. 5.2 Loss and efficiency analysis This subsection provides a concise, step-by-step description of the power loss calculation among the main components and a brief efficiency analysis of the suggested converter. Initially, the power loss of a MOSFET switching device can be written as follows (46) where Ps(mos) and Pcon(mos) are the MOSFET switching and conduction losses, respectively. Since each FB switch of this converter operates ZVS, the switching loss is optimally negligible. Therefore, we can consider only the conduction loss, and it can be stated as: (47) The variables and Rds(ON) represents the RMS current flowing through the MOSFET and the ON state resistance of the MOSFET, respectively. Hence, based on the experiential data and datasheet of the C3M0120090D MOSFET utilized in this study, the total power losses of four FB switches can be determined as follows: (48) The power dissipated by a diode can be calculated by multiplying its forward voltage drop, VF, by the average current, Id(avg), that flows through it during one switching cycle. Therefore, based on the datasheet of the IDH10S120 diode and the average current obtained from the experiment, the diode’s (four diodes) total losses may be determined. (49) The power dissipation of the B32776G4506K000 film capacitor utilized in this study can be computed using the following formula: (50) Hence, the total capacitor power loss will be the sum of four cascaded multiplier capacitors loss and one resonant branch capacitor loss: (51) The inductor loss is the sum of the core loss, PL(core), and the winding loss, PL(wind). The calculation of PL(core) involves multiplying the effective volume of the core, Ve, by the core loss per unit volume, P(c/v), according to the following formula: (52) Again, the inductor winding loss can be expressed as: (53) The variables IL(avg), IL(ac-rms), IL(pk-pk), and Rdc represent the average current, ac rms current, peak-peak ripple current magnitude, and winding dc resistance of the inductor, respectively. The VISHAY IHV15BZ500 and two BOURNS JW MILLER 1130-101K-RC devices are utilized in this study as the input boost inductor and resonant branch inductors, respectively. Therefore, based on the testing results and the inductor data sheet, the total inductor losses can be determined as follows: (54) Therefore, the total calculated power loss of the developed converter is (55) The experiment yielded a measured power loss of 16.80 W, which is marginally lower than the above-calculated power loss. The power loss for the diode and capacitor is determined based on a temperature of 25°C. Nevertheless, the temperature at the junction of these devices rises as power is dissipated, reducing the diode’s forward voltage drop and the capacitor’s equivalent series resistance (ESR). Consequently, there is a decrease in power loss. The loss distribution of the key apparatuses of the suggested converter is displayed in Fig 29. The switching loss is optimally negligible because every FB switch operates in a ZVS state. On the other hand, the switch conduction loss, which is 32%, is the highest contribution. The inductor and diode losses are close, 23% and 24%, respectively. The least contribution comes from the capacitor, which is 21%. Fig 30 demonstrates the efficiency of the FBRC converter, considering different load conditions and input voltages (40, 60, and 80 V). The input and output currents and voltages are measured using two oscilloscope current probes and multimeters to determine the converter’s efficiency. The system’s peak efficiency is 95.8% when a load of 400 W is connected, and an input voltage of 60 V is applied. This efficiency is achieved when the output voltage is set to 400 V. In addition, Fig 31 presents the effect of the duty ratio on the converter’s efficiency. The converter’s efficiency is also lower at a low duty ratio because the lower output voltage causes higher current resulting in more power loss. Again, at a higher duty ratio, converter efficiency is also lower. Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 29. Estimated power losses of different main components used in this converter. https://doi.org/10.1371/journal.pone.0306906.g029 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 30. Converter measured efficiency at various loads. https://doi.org/10.1371/journal.pone.0306906.g030 Download: PPT PowerPoint slide PNG larger image TIFF original image Fig 31. Measured efficiency vs duty cycle. https://doi.org/10.1371/journal.pone.0306906.g031 6. Conclusion High-gain dc-dc converters play a significant role in various renewable energy and other systems. This study introduces a novel ZVS full-bridge cascaded step-up dc-dc converter. In addition to comprehensive analytical analysis, a laboratory-scale prototype was designed, constructed, and subjected to experimental testing. The theoretical findings closely align with the observed experimental outcomes of the 500 W prototype converter. In the prototype implementation, high-performance SiC-based MOSFETs have been utilized as switching devices. Furthermore, the PID-based PWM control scheme and the resonant component have been employed to control the turn-off and turn-on operations of the FB switches from 25 to 100% load conditions facilitating zero-voltage switching (ZVS). The application of four such FB switches ensured complete soft-switching (zero switching loss). Additionally, the resonant technique leads to smaller passive components and reduces voltage stress on both active and passive devices. Consequently, this results in smaller and more cost-effective devices compared to other converters. Moreover, it offers less ripple in input current (5%) and output voltage (0.76%). From an efficiency standpoint, the converter achieves its maximum efficiency of 95.8% when operated at input and output voltages of 60 V and 400 V, respectively, with a load power of 400 W. The dc-dc converter proposed in this research achieves an excellent dc voltage conversion ratio (> 10) by preventing excessively high-duty cycle operation of the MOSFET switches, thereby limiting the maximum current flow through the active devices. Hence, the proposed FBRC converter is well-suited for systems generating low output voltage, making it particularly suitable for variable wide input ranges (tested from 40 V to 80 V), commonly found in low voltage systems like photovoltaic (PV), fuel cell (FC), and electric vehicles (EV). Acknowledgments The authors express their appreciation for the technical assistance provided by Dhaka University of Engineering & Technology, Gazipur, Bangladesh, and UM Power Energy Dedicated Advanced Centre (UMPEDAC), Universiti Malaya, Malaysia, in facilitating this research.
TI - A novel ZVS full-bridge cascaded step-up DC-DC converter with resonant auxiliary circuit for high voltage-gain applications
JF - PLoS ONE
DO - 10.1371/journal.pone.0306906
DA - 2024-08-15
UR - https://www.deepdyve.com/lp/public-library-of-science-plos-journal/a-novel-zvs-full-bridge-cascaded-step-up-dc-dc-converter-with-resonant-HAwWYB8aL3
SP - e0306906
VL - 19
IS - 8
DP - DeepDyve
ER -