TY - JOUR
AU - Kumar, Manoj
AB - (IJACSA) International Journal of Advanced Computer Science and Applications, An Integrated Architectural Clock Implemented Memory Design Analysis Ravi Khatwal Manoj Kumar Jain Research scholar Professor Department of computer science Department of computer science MLS University MLS University Udaipur, India Udaipur, India Abstract—Recently Low power consumption and Custom gradually increases is the major issue. The no. of transistors Memory design is major issue for embedded designer. Micro can be reduces and implements clock and materials design wind and Xilinx simulator implements SRAM design techniques that reduces data losses of SRAM. architecture and performs efficient simulation. These simulators A cell design architecture implementation method implements high performances and low power consumption of improves the SRAM performance and consumes low power. SRAM design. SRAM efficiency analyzed with 6-T architecture Cache implementation technique also implements high speed design and row/column based architectural design. We have data transfer scheme. Kuldar at el. [1] proposed a technique to analyzed clock implemented memory design and simulated with specific application. We have implemented clock based SRAM synthesize the local memory architecture of a clustered architecture that improves the internal clock efficiency of SRAM. accelerator using a phase-ordered approach. Merolla at el. [2] Architectural Clock implemented memory design 
TI - An Integrated Architectural Clock Implemented Memory Design Analysis
JF - International Journal of Advanced Computer Science and Applications
DO - 10.14569/ijacsa.2015.060717
DA - 2015-01-01
UR - https://www.deepdyve.com/lp/unpaywall/an-integrated-architectural-clock-implemented-memory-design-analysis-EBOTAvRQLs
DP - DeepDyve
ER -