TY - JOUR
AU - 
AB - (IJACSA) International Journal of Advanced Computer Science and Applications, Efficient Page Collection Scheme for QLC NAND Flash Memory using Cache 1 2 3 Seok-Bin Seo , Wanil Kim , Se Jin Kwon Department of Computer Engineering Kangwon National University Samcheok, South Korea Abstract—Recently, semiconductor companies such as prior to performing data renewal of a page [1]. Samsung, Hynix, and Micron, have focused on quad-level cell The biggest differences between QLC NAND flash (QLC) NAND flash memory chips, because of the increase in the memory and SLC/MLC/TLC NAND flash memories are the capacity of storage systems. The QLC NAND flash memory chip page/block size and performance. In a QLC NAND flash stores 4 bits per cell. A page in the QLC NAND flash memory memory, a page consists of 16 sectors, which is larger than consists of 16 sectors, which is two to four times larger than that that of conventional SLC/MLC/TLC NAND flash memory. of conventional triple-level cell flash NAND flash memory. Because of its large page size, when the QLC NAND flash Consequently, the read/write/erase operations of QLC NAND memory is applied to the current storage system directly, each flash memory are slow compared with those of page 
TI - Efficient Page Collection Scheme for QLC NAND Flash Memory using Cache
JO - International Journal of Advanced Computer Science and Applications
DO - 10.14569/ijacsa.2018.091164
DA - 2018-01-01
UR - https://www.deepdyve.com/lp/unpaywall/efficient-page-collection-scheme-for-qlc-nand-flash-memory-using-cache-E3c4LvwzUY
DP - DeepDyve
ER -