TY - JOUR
AU1 - Geurkov, Vadim
AU2 - Kirischian, Valeri
AU3 - Kirischian, Lev
AU4 - 
AB - XIX IMEKO World Congress Fundamental and Applied Metrology September 6−11, 2009, Lisbon, Portugal 1 2 3 Vadim Geurkov , Valeri Kirischian , Lev Kirischian Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada 1 2 3 vgeurkov@ee.ryerson.ca, vkirisch@ee.ryerson.ca, lkirisch@ee.ryerson.ca Abstract − When testing an analog-to-digital converter the one for the fault-free device. Their mismatch indicates that the DUT is faulty. (ADC) by automatic test equipment (ATE), the latter is capable of performing extensive processing of output Feeding inputs with the exhaustive sequence of stimuli increases fault coverage, but compaction of the output responses of the ADC. This allows detection of virtually any fault. However, the cost of ATE is quite high. As well, the response causes some errors to escape detection due to aliasing. With the size of signature equal to 16, the aliasing external bandwidth of ATE is normally lower than the internal bandwidth of the ADC being tested, which makes it rate is sufficiently low, such that the efficiency of the method is quite high. Because of these attractive features, difficult to accomplish at-speed testing. It is important, therefore, to embed test hardware into ADC itself. The signature analysis has gained considerable popularity. We will attempt 
TI - Signature Testing of Analog-To-Digital Converters
DO - 10.32920/21493938.v1
DA - 2024-04-03
UR - https://www.deepdyve.com/lp/unpaywall/signature-testing-of-analog-to-digital-converters-DdVkg7qzwt
DP - DeepDyve
ER -