TY - JOUR
AU1 - Xiang, Annie C.
AU2 - Cao, Tingting
AU3 - Gong, Datao
AU4 - Hou, Suen
AU5 - Liu, Chonghan
AU6 - Liu, Tiankuan
AU7 - Su, Da-Shung
AU8 - Teng, Ping-Kun
AU9 - Ye, Jingbo
AB - Abstract:We develop a custom Bit Error Rate test bench based on Altera's Stratix II GX transceiver signal integrity development kit, demonstrate it on point-to-point serial optical link with data rate up to 5 Gbps, and compare it with commercial stand alone tester. The 8B/10B protocol is implemented and its effects studied. A variable optical attenuator is inserted in the fibre loop to induce transmission degradation and to measure receiver sensitivity. We report comparable receiver sensitivity results using the FPGA based tester and commercial tester. The results of the FPGA also shows that there are more one-to-zero bit flips than zero-to-one bit flips at lower error rate. In 8B/10B coded transmission, there are more word errors than bit flips, and the total error rate is less than two times that of non-coded transmission. Total error rate measured complies with simulation results, according to the protocol setup.
TI - High-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers
JF - Physics
DO - 10.5170/cern-2009-006.471
DA - 2024-01-28
UR - https://www.deepdyve.com/lp/arxiv-cornell-university/high-speed-serial-optical-link-test-bench-using-fpga-with-embedded-DQqppufpRx
VL - 2024
IS - 2401
DP - DeepDyve
ER -