TY - JOUR
AU - Ning, Li
AB - A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled oscillator (VCO) gain without poisoning phase noise and reference spur suppression performance. An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application. It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-m RF CMOS technology. The measured tuning range is from 4.2 to 5.9 GHz. It achieves a low phase noise of 99 dBc/Hz @ 1 MHz offset from a 5.5 GHz carrier.
TI - A multiple-pass ring oscillator based dual-loop phase-locked loop
JF - Journal of Semiconductors
DO - 10.1088/1674-4926/30/10/105014
DA - 2009-10-01
UR - https://www.deepdyve.com/lp/iop-publishing/a-multiple-pass-ring-oscillator-based-dual-loop-phase-locked-loop-CiSmOKcfv3
SP - 105014
VL - 30
IS - 10
DP - DeepDyve
ER -