TY - JOUR
AU1 - Shahrabadi, Salimeh
AB - Recently, several studies were done on SRAM bitcells at different supply‐voltages; upper, near or lower to threshold voltage. To the best of the author's knowledge, none of them discussed at threshold supply‐voltage with proper subthreshold operations and Nano/Pico power‐dissipations, hence this paper decides to investigate challenges and solutions of designing at VDD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ =  Vth ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$, because this voltage will lead to having lower power consumptions. This research applies power‐gating technique to adjust VDD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ on Vth ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$, and also utilises output‐inverter to set Logic 1 at VDD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$. Although ‘power‐gating’ and ‘output‐inverter’ were used in other works, this study renders specific points about them. In fact, the ability of power‐gating technique in adjusting VDD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ on Vth ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$ without any instabilities in bitcell operation was not reported before, as well as, the idea of employing output‐inverter in read path for setting Logic‐1 at VDD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$. It also proposed SNM% as a useful figure‐of‐merit. The goal of this study is not to present new circuits for bitcell, but is to investigate challenges and solutions of working under ‘VDD=Vth ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}={\mathbf{V}}_{\mathbf{t}\mathbf{h}}$’ which these solutions can lead to having an optimum bitcell.
TI - Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell
JF - "IET Circuits, Devices & Systems"
DO - 10.1049/cds2.12126
DA - 2022-11-01
UR - https://www.deepdyve.com/lp/wiley/challenges-and-solutions-of-working-under-threshold-supply-voltage-for-ApJubOA3za
SP - 569
EP - 580
VL - 16
IS - 8
DP - DeepDyve
ER -