TY - JOUR
AU - 
AB - This study deals with electrical instability under bias stress in pentacene-based transistors with gate dielectrics deposited by a lamination process. Mylar film is laminated onto a polyethylene terephtha- late (PET) substrate, on which aluminum (Al) gate is deposited, followed by evaporation of organic semiconductor and gold (Au) source/drain contacts in bottom gate top contact configuration (Device 1). In order to compare the influence of the semiconductor/dielectric interface, a second organic tran- sistor (Device 2) which is different from the Device 1 by the deposition of an intermediate layer of po- lymethyl methacrylate (PMMA) onto the laminated Mylar dielectric and before evaporating pentacene layer is fabricated. The critical device parameters such as threshold voltage (V ), subthreshold slope (S), mobility (µ), onset voltage (V ) and I /I ratio have been studied. The results showed that the on on off recorded hysteresis depend on the pentacene morphology. Moreover, after bias stress application, the electrical parameters are highly modified for both devices according to the regimes in which the tran- sistors are operating. In ON state regime, Device 1 showed a pronounced threshold voltage shift asso- ciated to charge trapping, while keeping the µ, I current and S minimally affected. Regardless 
TI - Electrical Instability in Pentacene Transistors with Mylar and PMMA/Mylar Gate Dielectrics Transferred by Lamination Process
JF - Journal of Applied Mathematics and Physics
DO - 10.4236/jamp.2016.47125
DA - 2016-01-01
UR - https://www.deepdyve.com/lp/unpaywall/electrical-instability-in-pentacene-transistors-with-mylar-and-pmma-AgzZ4t4SFe
DP - DeepDyve
ER -