TY - JOUR
AU - Mourad, Samiha
AB - This study presents a novel design approach combining wave 
pipelining and self reset logic, which provides an elegant 
solution at high-speed data throughput with significant savings in 
power and area as compared with other dynamic CMOS logic 
implementations. To overcome some limitations in SRL art, we 
employ a new SRL family, namely, dual-rail self reset logic with 
input disable (DRSRL-ID).  These gates depict fairly constant 
timing parameters, specially the width of the output pulse, for 
varying fan-out and logic depth, helping accommodate process, 
supply voltage,  and temperature variations (PVT). These 
properties simplify the implementation of wave pipelined circuits. 
General timing analysis is provided and compared with previous 
implementations. Results of circuit implementation are presented 
together with conclusions and future work.
TI - Wave Pipelining Using Self Reset Logic
JF - VLSI Design
DO - 10.1155/2008/738983
DA - 2008-04-15
UR - https://www.deepdyve.com/lp/wiley/wave-pipelining-using-self-reset-logic-AW7e07BKO8
VL - 2008
IS - 
DP - DeepDyve
ER -